Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems

Gaona, Epifanio; Titos-Gil, Ruben; Fernández, J.F.; Acacio, Manuel E.

doi:10.1007/s11227-013-1072-y

Cited by 4 publications

(1 citation statement)

References 28 publications

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“…L Hang adopts a dynamic voltage/frequency scaling mechanism for communication line in interconnection structure, which is based on the usage of the interconnection that dynamically adjusts the voltage of communication line for low power consumption [8]. Considering that off-chip memory access brings latency and power consumption, multi-core processor often integrates a certain number of on-chip storage unit to improve the speed of memory access, and to reduce the power consumption [9][10]. On-chip memory optimization mainly involves the reasonable allocation of on-chip memory to reduce the off-chip memory access.…”

Section: Related Workmentioning

confidence: 99%

Low Power Gated-Clock Design for Multi-core DSP Based SDR Platform

Xu¹,

An²,

Wang³

et al. 2016

IJUNESST

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Section: Related Workmentioning

confidence: 99%

Low Power Gated-Clock Design for Multi-core DSP Based SDR Platform

Xu¹,

An²,

Wang³

et al. 2016

IJUNESST

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Fast and efficient commits for Lazy-Lazy hardware transactional memory

2015

Self Cite

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Transactional Memory (TM) is a compelling alternative to simplify multi-threaded programming that traditionally relies on error-prone lockbased synchronization for implementing cooperative tasks. Lazy-Lazy hardware TM is one of the most efficient schemes in today's Hardware TM systems (HTMs). Nonetheless, the commit protocol in these systems has severe impact on performance and energy. The SEQ in Scalable TCC implementation (STCC-SEQ) is the most popular and efficient commit protocol to date. In this paper, we propose GCommit, a cost-effective hardware-based STCC-SEQ protocol. GCommit employs a G-Arbiter microarchitecture for achieving minimal-latency and high-efficient commits. We implement G-Arbiter with a standard 45 nm cell library. For a target 16-core CMP, a G-Arbiter just represents 0.07% of the whole on-chip area, requiring marginal energy consumption. Full-system simulations of the target system with the STAMP benchmarks show that GCommit achieves average reductions of 15.7% and 13.7% in execution time and energy, respectively, when compared with STCC-SEQ.

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Power Efficient Hardware Transactional Memory

Stephen

Dubois

2016

ACM Trans. Archit. Code Optim.

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(TM) is no longer just an academic interest as industry has started to adopt the idea in its commercial products. In this paper, we propose Dynamic Transaction Issue (DTI), a new scheme that can be easily implemented on top of existing Hardware TM (HTM) systems, provided additional messages. Instead of wasting power and energy in transaction aborts, Dynamic Transaction Issue puts a processor core into a low-power state when there is a reasonable suspicion that the current transaction running on it will be aborted soon in the future. We have implemented Dynamic Transaction Issue on a cycle-accurate simulator of a multicore processor system with out-of-order superscalar cores, augmented with a power package and a TM package which add accurate dynamic power estimates and a TM framework to the simulator. Our simulation results show that Dynamic Transaction Issue can achieve energy savings up to 37% from the energy consumption of a base machine with no mechanism to suppress useless aborts. We also compare Dynamic Transaction Issue with various alternative hardware TM mechanisms.

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Selective dynamic serialization for reducing energy consumption in hardware transactional memory systems

Cited by 4 publications

References 28 publications

Low Power Gated-Clock Design for Multi-core DSP Based SDR Platform

Low Power Gated-Clock Design for Multi-core DSP Based SDR Platform

Fast and efficient commits for Lazy-Lazy hardware transactional memory

Power Efficient Hardware Transactional Memory

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