TMbox: A Flexible and Reconfigurable 16-Core Hybrid Transactional Memory System

Abstract

In this paper we present the design and implementation of TMbox: An MPSoC built to explore tradeoffs in multicore design space and to evaluate parallel programming proposals such as Transactional Memory (TM). Our flexible system, comprised of MIPS R3000-compatible cores is easily modifiable to study different architecture, library and operating system extensions. For this paper we evaluate a 16-core Hybrid Transactional Memory implementation based on the TinySTM-ASF proposal on a Virtex-5 FPGA and we accelerate three benchmarks written to investigate TM.

A Low-Overhead Profiling and Visualization Framework for Hybrid Transactional Memory

“…A completely modifiable architecture would help us change the ISA and the software toolchain. The TMbox system [12] features an open-source Hybrid TM implementation of up to 16 MIPS soft processor cores interconnected with a bi-directional ring bus on a Virtex5-155t FPGA of the BEE3 prototyping platform [17].…”

“…This approach enables using the fast TM hardware whenever it is possible, but meanwhile to have an alternative way of processing transactions that are more complex or too large to make use of the TM hardware. The hardware TM implementation supports lazy commits: Modifications made to the transactional lines are not sent to memory until the whole transaction is allowed to successfully commit [12]. However, TinySTM supports switching between eager and lazy commit and locking schemes as we will look into with software transactions in Section IV-B.…”

“…ATLAS and later Configurable TM were the first systems to support hardware TM on FPGA [8], [9]. Hardware acceleration proposals by using Bloom filters for TM were also investigated [10], [11], as well as Hybrid TM on FPGA [12].…”

A multicore emulator with a profiling infrastructure for transactional memory on FPGA

“…The hardware TM implementation supports lazy commits: Modifications made to the transactional lines are not sent to memory until the whole transaction is allowed to successfully commit [122]. However, TinySTM supports switching between eager and lazy commit and locking schemes as we will look into with software transactions later in Section 4.4.2.…”

“…The The programming model of the underlying TMbox system [122] is comparable to the TCC model [54]. The monitoring techniques used in this work are in some parts similar to the TAPE [21] system.…”