A robust and write bit-line free sub-threshold 12T-SRAM for ultra low power applications in 14 nm FinFET technology

Karamimanesh, Mehrzad; Abiri, Ebrahim; Hassanli, Kourosh; Salehi, Mohammad Reza; Darabi, Abdolreza

doi:10.1016/j.mejo.2021.105185

Cited by 26 publications

(8 citation statements)

References 24 publications

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“…28,33 Furthermore, PTM model for high-performance silicon-based MOSFET nano-device incorporating high-k/metal gate and stress effect at the same physical gate length are used. 26,28,33 The characteristics of the input structure parameters related to the designs based on other GAA CNT-MOSFET, TG CNTFET and Si-MOSFET technologies can be defined by the user with the range of values used for them which brief descriptions are listed in Table II. It is worthwhile to mention that all well-known counterpart asymmetrical bit-cells designs 19,20 and Ref.…”

Section: Simulation Results Comparative Analysis and Discussionmentioning

confidence: 99%

“…The one-sided or single bit-line (BL) scheme SRAM structure is one of the most basic blocks in the design of circuits with special applications which aim the low power and reduce complexity and consumption area in nanotechnology-scale designs. 26,27 The gate z E-mail: a.darabi@sutech.ac.ir diffusion input method based on gate-all-around (GAA) carbon nano-tube (CNT)-MOSFET technology (GAA CNT-GDI) is a logic design methodology for reducing power consumption, propagation delay under process, voltage temperature (PVT) corners, enhanced hazard tolerance, and maintaining low area complexity in digital combinatorial circuits. 28 Based on RHBD approach, a new structure of ultra-low power radiation-hardened single-ended (UPRHSE) 11T-SRAM bit-cell with inherent SNU and DNU prevention and also self-recover capabilities to be applied in low earth orbit (LEO) radiation-prone environments, where limited-energy resources has been proposed.…”

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confidence: 99%

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Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Darabi¹,

Salehi²,

Abiri³

2022

ECS J. Solid State Sci. Technol.

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We propose a novel design of an ultra-low power radiation-hardened single-ended (UPRHSE) SRAM bit-cell using the GAA CNT-GDI method. In the structure of bit-cell to improve read-/hold-stability and expand write-ability several schemes have been used such as asymmetric virtual ground gating, built-in read-assist and the multi-diameter/chirality for CNTs. Also, to investigate single/double upsets, injection circuit model using the structure of the T-connected pseudo resistors is proposed. The results of extensive Monte-Carlo simulations to evaluate the proposed bit-cell indicate larger noise margins, acceptable yield, less sensitivity to PVT variations, and higher critical charge. Moreover, the suggested bit-cell has more robustness to soft errors with high reliability of data storage in the presence of critical voltage conditions, and better results in other comprehensive figures of merit as compared to state-of-the-art bit-cells in the 16 nm technology. Finally, the proposed bit-cell in a real application is used to store data from two-layer quick-response code-based in terrestrial environments. The results show better performance of the bit-cell in terms of a comprehensive FoM, which provides more effective trade-off between the hardware efficiency and quality metrics to evaluate the appropriate accuracy in the pixel-by-pixel image as compared to other well-known counterpart designs.

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Section: Simulation Results Comparative Analysis and Discussionmentioning

confidence: 99%

mentioning

confidence: 99%

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Darabi¹,

Salehi²,

Abiri³

2022

ECS J. Solid State Sci. Technol.

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“…SRAMs are therefore produced at a high speed and density. As a fall in supply voltage (VDD) results in a quadratic or linear reduction in dynamic or static power, the first challenge is to maintain adequate levels of dynamic power [5]. However, a decrement in V DD also causes an increment in leakage current, which ultimately raises total power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

Kumar,

Lorenzo

2023

Eng. Res. Express

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Many scientists are working to develop a static random-access memory (SRAM) cell that used little power and has good stability and speed. This work introduces a fin field effect transistor developed SRAM cell with 10 transistors (10T FinFET SRAM). A cross connected standard inverter and schmitt-trigger inverter is used in the proposed 10T FinFET SRAM cell. We introduce the schmitt trigger based SRAM cell with single-ended read decoupled and feedback-cutting approaches to enhance the static noise margin (SNM) and access time of the SRAM cell. The proposed cell’s power utilization is decreased with the help of stacked N-FinFETs. For determining the relative performance of the proposed 10T FinFET SRAM cell design in terms of fundamental design metrics, it has also been compared with some of the current SRAM cells, including 6T, SBL9T SRAM, 10T SRAM, and DS10T SRAM. The simulation results at 0.6V demonstrate that the suggested design achieves low power utilization when Reading, writing and hold modes of operation in comparison to the aforementioned bit cells. It maintains a high SNM during all operations. The suggested cell is the one with fastest read access. The simulation is carried out with cadence tool using FinFET 18nm technology.

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“…This is because dynamic power and leakage power reduce quadratically and linearly (to the first order), respectively, with V DD reduction. 3 In literature, 1,[4][5][6][7][8][9] researchers have designed and presented their proposed SRAM cell in the near or subthreshold region to gain the advantage of the attractive method of V DD scaling. Nonetheless, with an aggressive decrease in technology nodes, subthreshold leakage current, threshold voltage, and manufacturing process, voltage, and temperature (PVT) variations highly degrade, 10 reducing static noise margins (SNMs) of SRAM cells during read and write operations.…”

Section: Introductionmentioning

confidence: 99%

A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications

Abbasian

Gholipour

2022

Circuit Theory & Apps

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The design of power‐efficient SRAM cells is necessary for biomedical applications such as body area networks (BANs) to extent their battery life. SRAM cell's power consists of two main components, including leakage power and dynamic power, in which the former overcomes the latter in advanced technology. This paper presents a low‐leakage single‐bitline 9T (L2SB9T) SRAM cell. The proposed design is free from read‐disturbance issue and eliminates writing “1” problem. The results are carried out by utilizing HSPICE and 16‐nm CMOS PTM at a 0.7 V, 25°C, and under severe PVT variations. The proposed L2SB9T SRAM cell is comprehensively compared with other recently published SRAM cells including conventional 6T, write/read enhanced 8T (WRE8T), transmission‐gate 9T (TG9T), read‐disturb‐free 9T (RDF9T), fully differential 10T (Chang10T), data‐independent read port 10T (DIRP10T), and single‐bitline 11T (SB11T). It shows at least 1.26X/1.07X/1.01X improvement in read static noise margin (RSNM)/write static noise margin (WSNM)/write margin (WM). Furthermore, the leakage power is reduced by the proposed cell, at least 1.137X. Moreover, the suggested cell consumes the third/second best dynamic read/write power, which is 1.42X/1.37X lower than that of conventional 6T SRAM cell. The proposed L2SB9T SRAM cell performs its read/write operation reliably by showing at least 1.71X narrower speared in RSNM compared to the best SRAM cell and third best WM variability. For all these improvements, the proposed L2SB9T SRAM cell incurs a 4.20X/1.06X/1.808X penalty in read delay/write delay/layout area when compared with the best SRAM cells, that is, the Chang10T/6T/6T.

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A robust and write bit-line free sub-threshold 12T-SRAM for ultra low power applications in 14 nm FinFET technology

Cited by 26 publications

References 24 publications

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Wrap-Gate CNT-MOSFET Based SRAM Bit-Cell with Asymmetrical Ground Gating and Built-In Read-Assist Schemes for Application in Limited-Energy Environments

Design of highly stable, high speed and low power 10T SRAM cell in 18-nm FinFET technology

A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications

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