A regularity-driven fast gridless detailed router for high frequency datapath designs

Abstract

We present a new detailed routing methodology specifically designed for datapath layouts. In typical state-of-the-art microprocessor designs, datapaths comprise about 70% of the logic (excluding caches). Although research on datapath placement and global routing has been reported, very little research has been reported in the area of detailed routing for datapaths.Datapaths typically comprise regular bit-slices which are replicated. We define a net-cluster, which is collection of similarly structured nets present across different bit-slices. We introduce two clustering schemes (Footprint-driven clustering and Instancedriven clustering) to extract such net-clusters. Then, we perform a strap-based routing on exactly one member net of each net-cluster (in a single representative bit-slice). Next, for each net, we propagate its route to all other nets in its net-cluster. Our algorithm is unique in that it performs the detailed routing on a single bit-slice, and infers the routing for all bit-slices using the notion of net clusters.We demonstrate at least 6¢ speed gains for industrial 32 and 64-bit datapath designs. The regularity of the routes across the bitslices results in more predictable timing characteristics for the resulting datapath layout.

Data-path layout design inside SOC

“…One of the most difficult problems is datapath layout design. In typical state-of-the-art microprocessor designs, data-paths comprise about 70% of the logic (excluding caches) [30]. However, data-path design is typically done manually, and is often custom style 1311.…”