A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems

Ro, Duckhoon; Min, Chang-Hong; Kang, Myounggon; Chang, Ik Joon; Lee, Hyung Min

doi:10.3390/s20010171

Cited by 11 publications

(13 citation statements)

References 17 publications

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“…For all the Spice simulations, the sensor was modeled by an ideal current source in parallel with capacitor C det which values vary up to 2 pF. The Transistors were placed symmetrically, biased and designed by keeping the ratio

sufficiently high in order to optimize mismatch along with the stability of other analog performance such as the gain-bandwidth product GBW [ 41 , 43 ]. The CSA input’s transistor size and biasing current were optimized for matching the input capacitance to the target sensor’s capacitance [ 26 ].…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

“…The feedback equivalent resistor (R F ) was implemented by associating the drain-source resistance of two N-channel MOSFETs (M F and M p on Figure 3 ) device biased to be in the triode strong inversion region. Under this condition, the parallel noise was minimized to a large extent; thus, the circuit is stable and continuously sensitive and can be maintained in this condition without adjustment for spectroscopy purposes [ 16 , 40 , 41 , 43 ]. Thus, with that technique, we achieved up to 3.542 MΩ feedback equivalent resistances, which guarantee a phase margin of 82°.…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

“…The noise corner frequency fc, which is the frequency at which the asymptotes of the flicker and thermal noise components cross was identified as the frequency range over which the CSA op-amp noise is dominated by either the 1/f or the thermal noise components [ 36 , 37 , 38 , 39 , 40 , 41 , 42 , 43 , 44 , 45 , 46 , 47 , 48 , 49 ]. In agreement with this definition [ 36 ], the noise corner frequency of our design has been controlled to be 652.9 MHz.…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

“…Moreover, while layout the design, mismatch reduction helps in reducing the fluctuation of V TH taking into account the trade-off between drain-induced barrier lowering (DIBL) mitigation and gate leakage reduction [ 42 ]. Therefore, if the transistor works in this region, increasing its gate width too much worsens the noise, because it leads to more gate capacitance without improving the transconductance [ 6 , 41 , 43 ]. The total gate capacitance, which optimizes the different components of ENC, is obtained by solving the equations

and

respectively [ 6 ].…”

Section: Design Philosophy and Materialsmentioning

confidence: 99%

See 3 more Smart Citations

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Jérôme

Evariste

Bernard

et al. 2021

Sensors

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The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

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Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

and

respectively [ 6 ].…”

Section: Design Philosophy and Materialsmentioning

confidence: 99%

See 2 more Smart Citations

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Jérôme

Evariste

Bernard

et al. 2021

Sensors

View full text Add to dashboard Cite

show abstract

“…Furthermore, radiation influences for unit circuits, for instance, bandgap reference circuit and bipolar CMOS (BiCMOS) amplifier, were analyzed in terms of output direct current (DC) voltage balance, spurious-free dynamic range (SFDR), etc. [ 11 , 12 , 13 , 14 , 15 ]. Similar to the developed circuits for space environments, suitable radiation hardened readout circuits for NPP conditions have become more highly required in these days.…”

Section: Introductionmentioning

confidence: 99%

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

Lee

Cho

Unruh

et al. 2020

Sensors

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According to the continuous development of metal-oxide semiconductor (MOS) fabrication technology, transistors have naturally become more radiation-tolerant through steadily decreasing gate-oxide thickness, increasing the tunneling probability between gate-oxide and channel. Unfortunately, despite this radiation-hardened property of developed transistors, the field of nuclear power plants (NPPs) requires even higher radiation hardness levels. Particularly, total ionizing dose (TID) of approximately 1 Mrad could be required for readout circuitry under severe accident conditions with 100 Mrad around a reactor in-core required. In harsh radiating environments such as NPPs, sensors such as micro-pocket-fission detectors (MPFD) would be a promising technology to be operated for detecting neutrons in reactor cores. For those sensors, readout circuits should be fundamentally placed close to sensing devices for minimizing signal interferences and white noise. Therefore, radiation hardening ability is necessary for the circuits under high radiation environments. This paper presents various integrated circuit designs for a radiation hardened charge-sensitive amplifier (CSA) by using SiGe 130 nm and Si 180 nm fabrication processes with different channel widths and transistor types of complementary metal-oxide-semiconductor (CMOS) and bipolar CMOS (BiCMOS). These circuits were tested under γ–ray environment with Cobalt-60 of high level activity: 490 kCi. The experiment results indicate amplitude degradation of 2.85%–34.3%, fall time increase of 201–1730 ns, as well as a signal-to-noise ratio (SNR) of 0.07–11.6 dB decrease with irradiation dose increase. These results can provide design guidelines for radiation hardening operational amplifiers in terms of transistor sizes and structures.

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Enhancement of nuclear radiation shielding properties of silicone rubber with γ‐ray irradiation induced graphene oxide modified carbonyl iron powder hybrid fillers

Meng

Chai

et al. 2023

J of Applied Polymer Sci

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In this study the graphene oxide modified carbonyl iron (GO‐CI) was prepared by γ‐ray irradiation, which was added to silicone rubber composites to enhance the nuclear radiation shielding performances. X‐ray diffraction (XRD) characterization result showed the structure and morphology of the obtained GO‐CI nanocomposites. The mixture of GO/CI and the hybrid GO‐CI were individually incorporated into the vinyl‐terminated polydimethylsiloxane (Vi‐PDMS) to prepare referenced SR/GO/CI and SR/GO‐CI composites. Compared with SR/GO/CI, the SR/GO‐CI exhibited better thermal conduction and mechanical recovery properties. Moreover, the γ‐ray radiation shielding ability of SR/GO‐CI is much higher than that of pristine SR/GO/CI. CI particles are coated by GO nanosheets to increase surface area to prevent sedimentation of CI. It implies that SR‐GO/CI composite would have potential application as the radiation hardening material with thermal conductive and nuclear radiation shielding function.

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A Radiation-Hardened SAR ADC with Delay-Based Dual Feedback Flip-Flops for Sensor Readout Systems

Cited by 11 publications

References 17 publications

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Integrated Circuit Design for Radiation-Hardened Charge-Sensitive Amplifier Survived up to 2 Mrad

Enhancement of nuclear radiation shielding properties of silicone rubber with γ‐ray irradiation induced graphene oxide modified carbonyl iron powder hybrid fillers

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