A Predictive Synchronizer for Periodic Clock Domains

Frank, Uri; Ginosar, Ran

doi:10.1007/978-3-540-30205-6_42

Cited by 10 publications

(12 citation statements)

References 14 publications

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“…Since ߜ is usually not known to the system designer, a method for adaptive delay learning is implemented. Previous works on adaptive synchronization [7]- [11] do not take ߜ into consideration and consequently may be unable to achieve the maximum ‫.ܨܤܶܯ‬ Figure 18. Graphical representation of solution of (15) The principle of the adaptive delay unit is shown in Figure 19 and consists of a variable delay and delay control block that are independent of the synchronizer.…”

Section: Maximizing Mtbfmentioning

confidence: 99%

“…In Section 4 we develop a formula for ‫ܨܤܶܯ‬ in a general coherent clock case and an optimality condition for minimum failure rate. In section 5 we show the conditions for achieving that minimum and explain why previous publications [7]- [11] on adaptive synchronization do not provide such optimality. Section 6 presents the case study of a synchronization failure in a Soc, as discussed at the beginning of this introduction, showing solutions to achieve the optimal condition and section 7 concludes the work.…”

Section: Introductionmentioning

confidence: 98%

“…Note that some cases of the loosely synchronous clocks may be either coherent or non-coherent, and hence it is impossible to unify the two different classifications. It is widely believed that loosely synchronous clock domains may be synchronized using either a special purpose synchronizer designed for each of the special cases(e.g., [7]- [11]), or using a brute-force ܰ-flip-flop synchronizer of the type designed for asynchronous domains [2] [3] [4] [19]. …”

Section: Introductionmentioning

confidence: 99%

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MTBF Estimation in Coherent Clock Domains

Beer

Ginosar

Dobkin

et al. 2013

2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems

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Abstract-Special synchronizers exist for special clock relations such as mesochronous, multi-synchronous and ratiochronous clocks, while variants of N-flip-flop synchronizers are employed when the communicating clocks are asynchronous. N-flip-flop synchronizers are also used in all special cases, at the cost of longer latency than when using specialized synchronizers. The reliability of N-flip-flop synchronizers is expressed by the standard MTBF formula. This paper describes cases of coherent clocks that suffer of a higher failure rate than predicted by the MTBF formula; that formula assumes uniform distribution of data edges across the sampling clock cycle, but coherent clocking leads to drastically different situations. Coherent clocks are defined as derived from a common source, and phase distributions are discussed. The effect of jitter is analyzed, and a new MTBF expression is developed. An optimal condition for maximizing MTBF and a circuit that can adaptively achieve that optimum are described. We show a case study of metastability failure in a real 40nm circuit and describe guidelines used to increase its MTBF based on the rules derived in the paper.

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Section: Maximizing Mtbfmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 98%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

MTBF Estimation in Coherent Clock Domains

Beer

Ginosar

Dobkin

et al. 2013

2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems

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“…There is no correlation between the frequencies of the clocks, but the frequency of each clock is maintained. They can be synchronized through a prediction of a synchronization failure [10,11].…”

Section: Introductionmentioning

confidence: 99%

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Song¹,

Park²,

Lee³

et al. 2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-For the performance-efficient integration of IPs on an SoC utilizing heterochronous multi-clock domains, we propose a synchronization scheme that causes low latency overhead when data are crossing clock boundaries. The proposed synchronization scheme is composed of a clock predictor and a synchronizer. The clock predictor of a sender clock domain produces a predicted clock that is used in a receiver clock domain to detect possible synchronization failures in advance. When the possible synchronization failures are detected, a synchronizer at the receiver delays data-capture times to avoid the possible synchronization failures. From the simulation of the proposed scheme through SPICE modeling using a Chartered 0.18 mm CMOS process, we verified the functionalities and timing behavior of the clock predictor and the synchronizer. The simulation results show that the clock predictor produces a predicted clock before a synchronization failure, and the synchronizer samples data correctly using the predicted clock.

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“…Adaptive phase compensation can be employed to connect multisynchronous domains, in which the phase drifts slowly over time [6] [7], as well as plesiochronous domains [8], where a very small frequency difference can be viewed as a phase drift. When two different-frequency clocks are used in the periodic case, a predictive synchronizer foresees and prevents contentions [9]. In the general asynchronous case, when the timing of input is unknown, the family of two flip-flop ("two-flop") synchronizers and two-clock FIFOs are employed.…”

Section: Introductionmentioning

confidence: 99%

Fast Universal Synchronizers

Dobkin

Ginosar

2009

Lecture Notes in Computer Science

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Abstract.Synchronization circuits are essential in multi-clock-domain systems-on-chip. The most well-known synchronizer consists of two sequentially connected flip-flops that should eliminate the propagation of metastability into the receiver clock domain. We first clarify how such a simple "two-flop" synchronizer can be used in the system, and analyze its performance, showing that the data cycle may be as long as 12 clock cycles. Novel faster synchronizers are described next and their use and improved performance are explained. The fast synchronizer enable shorter data cycles, measuring only 2 to 4 clock cycles. Synchronizer performance is also analyzed when the two communicating clock domains are separated by long interconnect, incurring additional latencies.

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A Predictive Synchronizer for Periodic Clock Domains

Cited by 10 publications

References 14 publications

MTBF Estimation in Coherent Clock Domains

MTBF Estimation in Coherent Clock Domains

Low Latency Synchronization Scheme Using Prediction and Avoidance of Synchronization Failure in Heterochronous Clock Domains

Fast Universal Synchronizers

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