A Predictable Execution Model for COTS-Based Embedded Systems

Pellizzoni, Rodolfo; Betti, Emiliano; Bak, Stanley; Yao, Gang; Criswell, John; Caccamo, Marco; Kegley, Russell

doi:10.1109/rtas.2011.33

Cited by 197 publications

(201 citation statements)

References 21 publications

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“…In addition it relies on accurate profiling of cache utilization, suitable assignment of the TDMA timeslots to the tasks' super-blocks, and imposes a restriction on where the tasks can be pre-empted. Pellizzoni et al (2011) introduced the PRedictable Execution Model (PREM) framework. This framework considers tasks as consisting of memory phases where they pre-fetch instructions and data, and execution phases where they execute with-out the need to access memory or I/O devices.…”

Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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In this paper, we introduce a multicore response time analysis (MRTA) framework, which decouples response time analysis from a reliance on contextindependent WCET values. Instead, the analysis formulates response times directly The additional material includes: Section 4: analysis for warmed-up caches and dynamic scratchpads (Sects. 4.3 and 4.2). Section 7: extensions to the task model, including RTOS and interrupts, shared software resources, and open systems and incremental verification. Section 8: presentation of a cycle-accurate multicore simulator. Section 9: evaluation of different local memory types (Sect. 9.2), a comparison between predictable and reference architectures (Sect. 9.3), and a verification of the precision of the analysis using results from the simulator (Sect. 9.4). 123Real-Time Syst from the demands placed on different hardware resources. The MRTA framework is extensible to different multicore architectures, with a variety of arbitration policies for the common interconnects, and different types and arrangements of local memory. We instantiate the framework for single level local data and instruction memories (cache or scratchpads), for a variety of memory bus arbitration policies, including: Round-Robin, FIFO, Fixed-Priority, Processor-Priority, and TDMA, and account for DRAM refreshes. The MRTA framework provides a general approach to timing verification for multicore systems that is parametric in the hardware configuration and so can be used at the architectural design stage to compare the guaranteed levels of real-time performance that can be obtained with different hardware configurations. We use the framework in this way to evaluate the performance of multicore systems with a variety of different architectural components and policies. These results are then used to compose a predictable architecture, which is compared against a reference architecture designed for good average-case behaviour. This comparison shows that the predictable architecture has substantially better guaranteed real-time performance, with the precision of the analysis verified using cycle-accurate simulation.

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Section: Related Work Assuming Different Application Modelsmentioning

confidence: 99%

An extensible framework for multicore response time analysis

et al. 2017

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“…In particular, in [3] the authors show that among the several resource access models analysed in that work, the one that performs best is the 3-phase task model. The 3-phase task model is a generalization of the PRedictable Execution Model (PREM) [1]. In PREM, tasks consist of two distinct phases: a memory phase and an execution phase.…”

Section: Related Workmentioning

confidence: 99%

“…Following this observation, computing an upper-bound on the interference suffered by each task and comparing it against a lower bound on the supply available in the problem window allows us to determine whether the system is schedulable or not. More precisely, if the maximum 1 The interference (I L k ) over a task τ k in an interval of length L is defined as the sum of all the time intervals in which τ k is ready but cannot execute due to the execution of higher priority tasks. 2 The supply in a time interval is the total amount of computation that could be performed within the interval.…”

Section: A Scheduling Policymentioning

confidence: 99%

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Schedulability analysis for global fixed-priority scheduling of the 3-phase task model

Maia

Nelissen

Nogueira

et al. 2017

2017 IEEE 23rd International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA)

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Scheduling real-time applications on general purpose multicore platforms is a challenging problem from atiming analysis perspective. Such platforms expose uncontrolledsources of interference whenever concurrent accesses to memoryare performed. The non-deterministic bus and memory accessbehavior complicates the estimations of applications 19 worst-caseexecution times (WCET).The 3-phase task model seems a good candidate to circumventthe uncontrolled sources of interference by isolating concurrentmemory accesses. A task is divided in three successive phases;first, the task loads its instruction and data in a local memory,then it executes nonpreemptively using those pre-loaded instructions and data, and finally, the modified data are pushed back tomain memory. Following this execution model, tasks never accessthe bus during their execution phase. Instead, all the bus accessesare performed during the first and third phases.In this paper, we focus on the global fixed-priority schedulingof the 3-phase task model. A new schedulability test is derivedby modelling the interference happening on the bus rather thanthe interference on the cores as in the state-ot-the-art techniques.The effectiveness of the test is evaluated by comparing it againstthe state-of-the-art. Abstract-Scheduling real-time applications on general purpose multicore platforms is a challenging problem from a timing analysis perspective. Such platforms expose uncontrolled sources of interference whenever concurrent accesses to memory are performed. The non-deterministic bus and memory access behavior complicates the estimations of applications' worst-case execution times (WCET).The 3-phase task model seems a good candidate to circumvent the uncontrolled sources of interference by isolating concurrent memory accesses. A task is divided in three successive phases; first, the task loads its instruction and data in a local memory, then it executes non-preemptively using those pre-loaded instructions and data, and finally, the modified data are pushed back to main memory. Following this execution model, tasks never access the bus during their execution phase. Instead, all the bus accesses are performed during the first and third phases.In this paper, we focus on the global fixed-priority scheduling of the 3-phase task model. A new schedulability test is derived by modelling the interference happening on the bus rather than the interference on the cores as in the state-ot-the-art techniques. The effectiveness of the test is evaluated by comparing it against the state-of-the-art.

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“…Co-scheduling of communication and computation [21] can further remove contention, and requires knowledge from the application structure. But with the increased complexity and non-determinism of processors, it is not easy to recognize a solution in the near future.…”

Section: Modelmentioning

confidence: 99%

An Execution Model for Fine-Grained Parallelism in Ada

Pinho¹,

Moore

Michell

et al. 2015

Lecture Notes in Computer Science

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Abstract. This paper extends the authors earlier proposal for providing Ada with support for fine-grained parallelism with an execution model based on the concept of abstract executors, detailing the progress guarantees that these executors must provide and how these can be assured even in the presence of potentially blocking operations. The paper also describes how this execution model can be applied to real-time systems.

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A Predictable Execution Model for COTS-Based Embedded Systems

Cited by 197 publications

References 21 publications

An extensible framework for multicore response time analysis

An extensible framework for multicore response time analysis

Schedulability analysis for global fixed-priority scheduling of the 3-phase task model

An Execution Model for Fine-Grained Parallelism in Ada

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