A Power-Efficient Mixed-Signal Smart ADC Design With Adaptive Resolution and Variable Sampling Rate for Low-Power Applications

Chen, Shih-Lun; Villaverde, Jocelyn F.; Lee, Ho-Yin; Chung, Danny Wen-Yaw; Lin, Ting-Lan; Tseng, Chih-Hao; Lo, Kuei-An

doi:10.1109/jsen.2017.2680472

Cited by 40 publications

(30 citation statements)

References 25 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Here, S(M −1) represents the summation of all of the lowerbit capacitors before the M-th weight capacitor. For example, considering the 4-th weight capacitor (M=4), Num(4)=8, the summation of all of the previous capacitors before the 4-th weight capacitor is : S(3)= Num(1) +Num (2) +Num(3)=1+2+4=7, finally, which satisfied the Equation (3). In general, in order to meet the N-bit conversion accuracy requirements, the number of unit capacitors applied to any N bits of the capacitor array must satisfy the above formula.…”

Section: Overall Functionmentioning

confidence: 99%

“…In order to ensure that the matching accuracy of the capacitor array is higher than 10 bit, it is necessary to satisfy σ (∆C/C) /100 ≤ 1/2 10 , so the minimum area of the unit capacitor is W × L ≥ 171.8µm 2 (20)…”

Section: Circuit Simulationmentioning

confidence: 99%

“…F Or the wearable electronic devices, low power consumption is its core indicator [1], [2]. Therefore, for its core chips, they all have lower power consumption requirements.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

Cen

Feng²,

Fan

et al. 2020

IEEE Access

View full text Add to dashboard Cite

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5+5+6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a 0.6µm standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm × 6.6mm. As for single channel SAR ADC, the area is 0.9mm × 2.0mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.

show abstract

Section: Overall Functionmentioning

confidence: 99%

Section: Circuit Simulationmentioning

confidence: 99%

See 1 more Smart Citation

Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

Cen

Feng²,

Fan

et al. 2020

IEEE Access

View full text Add to dashboard Cite

show abstract

“…These 3 previously proposed methods in literature provided a reliable reference for EEG compression in VLSI implementation. Recently, an adaptive resolution control [21] and a fuzzy resolution control [22] techniques for body signals have been proposed. Although these variable resolution control techniques can improve the compression rate efficiently, there is significant information that was lost in the body signal.…”

Section: Literature Reviewmentioning

confidence: 99%

VLSI Implementation of an Efficient Lossless EEG Compression Design for Wireless Body Area Network

Chen

Abu

et al. 2018

Applied Sciences

Self Cite

View full text Add to dashboard Cite

Data transmission of electroencephalography (EEG) signals over Wireless Body Area Network (WBAN) is currently a widely used system that comes together with challenges in terms of efficiency and effectivity. In this study, an effective Very-Large-Scale Integration (VLSI) circuit design of lossless EEG compression circuit is proposed to increase both efficiency and effectivity of EEG signal transmission over WBAN. The proposed design was realized based on a novel lossless compression algorithm which consists of an adaptive fuzzy predictor, a voting-based scheme and a tri-stage entropy encoder. The tri-stage entropy encoder is composed of a two-stage Huffman and Golomb-Rice encoders with static coding table using basic comparator and multiplexer components. A pipelining technique was incorporated to enhance the performance of the proposed design. The proposed design was fabricated using a 0.18 μm CMOS technology containing 8405 gates with 2.58 mW simulated power consumption under an operating condition of 100 MHz clock speed. The CHB-MIT Scalp EEG Database was used to test the performance of the proposed technique in terms of compression rate which yielded an average value of 2.35 for 23 channels. Compared with previously proposed hardware-oriented lossless EEG compression designs, this work provided a 14.6% increase in compression rate with a 37.3% reduction in hardware cost while maintaining a low system complexity.

show abstract

“…Therefore, it is quite difficult to perform well in both resolution and throughput for SAR ADCs [11]- [13]. Low/medium resolution application, low to medium speed, low-power and area are the important characteristics of SAR ADCs [14], [15]. The SAR logic performs binary search algorithm through all possible bits to determine each bit successively.…”

Section: Introductionmentioning

confidence: 99%

A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

et al. 2020

View full text Add to dashboard Cite

An energy efficient, low-power 10-bit asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter with the sampling frequency of 8 MS/s is presented for IEEE 802.15.1 IoT sensor based applications. An improved common mode charge redistribution algorithm is proposed for binary weighted SAR ADC. The proposed method uses available common mode voltage (V CM) level for SAR ADC conversion, and this method reduces the switching power by more than 12% without any additional DAC driver as compared to merged capacitor switching (MCS). Mathematical analysis of the proposed switching scheme results in the lower or equal power consumption for every digital code as compared to MCS. A two stage dynamic latched comparator with adaptive power control (APC) technique is used to optimize the overall efficiency. Furthermore, to minimize the digital part power consumption, a modified asynchronous SAR logic with digitally controlled delay cells is proposed. High efficiency with low power consumption makes it suitable for low power devices especially for IEEE 802.15.1 IoT sensor based applications. The proposed prototype is implemented using 1P6M 55 nm complementary metal-oxide-semiconductor (CMOS) technology. The measurement results that the proposed circuit achieves are 9.3 effective number of bits (ENOB) with signal-to-noise and distortion ratio (SNDR) of 58.05 dB at a sampling rate of 8 MS/s. The power consumption of SAR ADC is 45 µW when operated at 1 V power supply. INDEX TERMS Adaptive power control (APC), asynchronous logic, Bluetooth low energy (BLE), capacitive DAC (CDAC), IEEE 802.15.1 IoT sensors, low power consumption, successive approximation register (SAR) ADC.

show abstract

A Power-Efficient Mixed-Signal Smart ADC Design With Adaptive Resolution and Variable Sampling Rate for Low-Power Applications

Cited by 40 publications

References 25 publications

Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

Design of Capacitor Array in 16-Bit Ultra High Precision SAR ADC for the Wearable Electronics Application

VLSI Implementation of an Efficient Lossless EEG Compression Design for Wireless Body Area Network

A Design of 8 fJ/Conversion-Step 10-bit 8MS/s Low Power Asynchronous SAR ADC for IEEE 802.15.1 IoT Sensor Based Applications

Contact Info

Product

Resources

About