VLSI Implementation of an Efficient Lossless EEG Compression Design for Wireless Body Area Network

et al. 2021

Electronics

Self Cite

This paper presents a low-cost and high-quality, hardware-oriented, two-dimensional discrete cosine transform (2-D DCT) signal analyzer for image and video encoders. In order to reduce memory requirement and improve image quality, a novel Loeffler DCT based on a coordinate rotation digital computer (CORDIC) technique is proposed. In addition, the proposed algorithm is realized by a recursive CORDIC architecture instead of an unfolded CORDIC architecture with approximated scale factors. In the proposed design, a fully pipelined architecture is developed to efficiently increase operating frequency and throughput, and scale factors are implemented by using four hardware-sharing machines for complexity reduction. Thus, the computational complexity can be decreased significantly with only 0.01 dB loss deviated from the optimal image quality of the Loeffler DCT. Experimental results show that the proposed 2-D DCT spectral analyzer not only achieved a superior average peak signal–noise ratio (PSNR) compared to the previous CORDIC-DCT algorithms but also designed cost-efficient architecture for very large scale integration (VLSI) implementation. The proposed design was realized using a UMC 0.18-μm CMOS process with a synthesized gate count of 8.04 k and core area of 75,100 μm2. Its operating frequency was 100 MHz and power consumption was 4.17 mW. Moreover, this work had at least a 64.1% gate count reduction and saved at least 22.5% in power consumption compared to previous designs.

Section: Introductionmentioning

confidence: 99%

VLSI Implementation of a Cost-Efficient Loeffler DCT Algorithm with Recursive CORDIC for DCT-Based Encoder

Chung

et al. 2021

Electronics

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“…For efficiency, there were several studies that provided a significant cost-efficiency solution for device design. In wireless body sensor network (WSBN), a data reduction method was proposed for wireless devices in [ 18 ]. By using an adjacent signal, the device reduces the amount of data to improve power consumption during transmission.…”

Section: Introductionmentioning

confidence: 99%

A High-Accuracy and Power-Efficient Self-Optimizing Wireless Water Level Monitoring IoT Device for Smart City

Chi

et al. 2021

Sensors

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In this paper, a novel self-optimizing water level monitoring methodology is proposed for smart city applications. Considering system maintenance, the efficiency of power consumption and accuracy will be important for Internet of Things (IoT) devices and systems. A multi-step measurement mechanism and power self-charging process are proposed in this study for improving the efficiency of a device for water level monitoring applications. The proposed methodology improved accuracy by 0.16%–0.39% by moving the sensor to estimate the distance relative to different locations. Additional power is generated by executing a multi-step measurement while the power self-optimizing process used dynamically adjusts the settings to balance the current of charging and discharging. The battery level can efficiently go over 50% in a stable charging simulation. These methodologies were successfully implemented using an embedded control device, an ultrasonic sensor module, a LORA transmission module, and a stepper motor. According to the experimental results, the proposed multi-step methodology has the benefits of high accuracy and efficient power consumption for water level monitoring applications.

“…Furthermore, C.A. Chen et al provided a low power [ 14 ] and efficient compression algorithm [ 15 ] to increase the effectiveness of communication data without any loss. Body signals with noise are easy to confuse the diagnosis and misjudge the symptom is another challenge.…”

Section: Introductionmentioning

confidence: 99%

Low Cost AIP Design in 5G Flexible Antenna Phase Array System Application

Tung¹,

Liu²,

et al. 2020

Micromachines

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In this paper, a low cost 28 GHz Antenna-in-Package (AIP) for a 5G communication system is designed and investigated. The antenna is implemented on a low-cost FR4 substrate with a phase shift control integrated circuit, AnokiWave phasor integrated circuit (IC). The unit cell where the array antenna and IC are integrated in the same plate constructs a flexible phase array system. Using the AIP unit cell, the desired antenna array can be created, such as 2 × 8, 8 × 8 or 2 × 64 arrays. The study design proposed in this study is a 2 × 2 unit cell structure with dimensions of 18 mm × 14 mm × 0.71 mm. The return loss at a 10 dB bandwidth is 26.5–29.5 GHz while the peak gain of the unit cell achieved 14.4 dBi at 28 GHz.