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A 4channel 12-bit high-voltage radiation-hardened digital-to-analog converter for low orbit satellite applications.

This paper presents an external capacitor-less NMOS low-dropout (LDO) voltage regulator integrated with a standard CSMC 0.6 µm BiCMOS technology. Over a −55 • C to +125 • C temperature range, the fabricated LDO provides a stable and considerable amount of 3 A output current over wide ranges of output capacitance C OUT (from zero to hundreds of µF) and effective-series-resistance (ESR) (from tens of milliohms to several ohms). A low dropout voltage of 200 mV has been realised by accurate modelling. Operating with an input voltage ranging from 2.2 V to 5.5 V provides a scalable output voltage from 0.8 V to 3.6 V. When the load current jumps from 100 mA to 3 A within 3 µs, the output voltage overshoot remains as low as 50 mV without output capacitance, C OUT. The system bandwidth is about 2 MHz, and hardly changes with load altering to ensure system stability. To improve the load transient response and driving capacity of the NMOS power transistor, a buffer with high input impedance and low output impedance is applied between the transconductance amplifier and the NMOS power transistor. The total area of fabricated LDO voltage regulator chip including pads is 2.1 mm×2.2 mm.

Abstract-This paper presents a capacitive array optimization technique capable to improve the Spurious Free Dynamic Range (SFDR) and Signal-to-Noise-and-Distortion Ratio (SNDR) of Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) for smart sensor specifications. Monte Carlo simulation results show that the proposed optimization technique makes the SFDR, SNDR and (Signal-to-Noise Ratio) SNR better definitely concentrated, which means with a spread between maximum and minimum value much smaller than the one obtained by conventional calibration techniques. This gives rise to more stable and better performances. The averaged SFDR improves from 72.9 dB to 91.1 dB with σu = 0.4%, the 18.2 dB improvement required an off-line processing and a small digital logic circuits.

This paper proposes a 16-bit 6-channel high-voltage successive approximation register (SAR) ADC with an optimized 5+5+6 segmented capacitor array. The lower 10 bits of the capacitor array are all composed of unit capacitors without any calibration unit. Without calibration, the lower 10 bits of the capacitor array can ensure 10-bit conversion accuracy. Every of the upper 6 bits of the capacitor array contains a linearity calibration unit. The linearity error of the upper 6 bits is calibrated by the linearity calibration unit. The 16-bit is manufactured by a 0.6µm standard COMS process, and the total chip area of 6-channel ADC including pads is 6.6mm × 6.6mm. As for single channel SAR ADC, the area is 0.9mm × 2.0mm. The measurement results show that the effective conversion accuracy of the SAR ADC reaches 13 bits by using novel differential nonlinearity (DNL) and integral nonlinearity (INL) calibration methods. The power is 80mW, corresponding to a Figure of Merit (FOM) of 48 pJ/conv.-step.

Abstract-This paper presents mismatch calibration technique to improve the SFDR in a 14-bit successive approximation register (SAR) analog-to-digital converter (ADC) for wearable electronics application. Behavioral Monte-Carlo simulations are applied to demonstrate the effect of the proposed method where no complex digital calibration algorithm or auxiliary calibration DAC needed. Simulation results show that with a mismatch error typical of modern technology, the SFDR is enhanced by more than 20 dB with the proposed technique for a 14-bit SAR ADC.

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This paper presents a design of 14-bit 80 Msample/s pipelined ADC implemented in 0.35 m CMOS. A charge-sharing correction is proposed to remove the signal-dependent charge-injection, together with a low-jitter clock circuit, guaranteeing the high dynamic performance for the ADC. A scheme of capacitor-switching and a symmetrical layout technique minimizes capacitor mismatch, ensuring the overall linearity. The measured results show that the calibration-free ADC achieves an effective number of bits of 11.6-bit, spurious free dynamic range (SFDR) of 84.8 dB, signal-to-noise-and-distortion ratio (SNDR) of 72 dB, differential nonlinearity of C0.63/ 0.6 LSB and integrated nonlinearity of C1.3/ 0.9 LSB at 36.7 MHz input and maintains over 75 dB SFDR and 59 dB SNDR up to 200 MHz.