A power-efficient, low-noise, wideband, integrated CMOS preamplifier for LSO/APD PET systems

Binkley, D.M.; Puckett, B.S.; Casey, Michael; Saoudi, A.

doi:10.1109/23.856522

Cited by 53 publications

(26 citation statements)

References 22 publications

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“…The power consumption of the preamplifier/driver chip presented in this paper cannot be compared directly to the power consumption of the preamplifier in [6], since power is also needed for the driver part.…”

Section: Discussionmentioning

confidence: 98%

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Integrated low-noise low-power fast charge-sensitive preamplifier for avalanche photodiodes in JFET-CMOS technology

Pichler

Pimpl

Buttler³

et al. 2001

IEEE Trans. Nucl. Sci.

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To take advantage of the compactness of avalanche photodiode (APD) arrays, low-noise power-efficient fast charge-sensitive preamplifier chips with differential current drivers have been developed. A 16-channel and a single-channel version are available. The chips were adapted for low-capacitance 4 8 APD arrays produced by Hamamatsu, Japan. A mixed junction field-effect transistor (JFET)-CMOS production process yielded high-quality integrated JFETs for the input stage of the amplifier's folded cascode. Thus, the 1 -noise corner is kept at 4 kHz. The JFET has a transconductance of 11 mS at a drain current of 3 mA. The serial noise of the input transistor was found to be 0.8 nV Hz. The signal rise time of the driver outputs is 20 ns. The rms noise of the preamplifier was found to be 480 e with a 25-e pF noise slope for a shaping time of 50 ns. The serial input noise of the preamplifier is about 1.4 nV Hz from 200 kHz up to 40 MHz, and the 1 -noise corner is at 70 kHz. The power consumption is 30 mW per preamplifier, including the differential driver. The linearity is better than 1.3% over 48-dB dynamic range. For the 16-channel chip, the channel-to-channel gain variation is less than 3.5%. Performance similar to photomultiplier tubes can be achieved with APDs in combination with this integrated preamplifier chip.Index Terms-Aavalanche photodiode (APD), charge-sensitive preamplifier, junction field-effect transistor (JTET)-CMOS, lownoise preamplifier.

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Section: Discussionmentioning

confidence: 98%

“…Requirements may vary for different APD applications [6]. This paper describes the 16-channel charge-sensitive preamplifier chip, which was developed for a 32-channel APD array (4 8 pixels, 1.6 1.6 mm each, Hamamatsu Photonics, Japan) to be used in a high-resolution positron emission tomograph (PET).…”

mentioning

confidence: 99%

Integrated low-noise low-power fast charge-sensitive preamplifier for avalanche photodiodes in JFET-CMOS technology

Pichler

Pimpl

Buttler³

et al. 2001

IEEE Trans. Nucl. Sci.

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“…The methodology reduced design time by eliminating iterative, trial-and-error sizing simulations and directly included dc mismatch, often excluded in circuit simulations. Elements of the design methodology were also used for a power-efficient, low-noise CMOS preamplifier having measured input-referred noise voltage of 0.65 nV/Hz 1/2 [21] and a micropower, direct-conversion, very-low-frequency (VLF) single-chip CMOS receiver operating at a supply current of 80 µA [22]. The methodology was not described for the previous circuits, but is described here and illustrated through the design of three simple, 0.5-µm CMOS OTA's.…”

Section: Introductionmentioning

confidence: 99%

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

Binkley

Blalock

Rochelle³

2006

Analog Integr Circ Sig Process

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This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-µm operational transconductance amplifiers having equal 50-µA bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, −3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz 1/2 , and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes.

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“…ENC and signal slope at the shaping filter output have been evaluated using custom Matlab and Simulink functions for shaping time constants between 10ns and 35ns and for integration stages of first and second order. The noise parameters of the preamplifier presented in [3] has been used to evaluate ENC. The simulation results are presented in Tables I and II.…”

Section: Cr-rc N Filter Specificationsmentioning

confidence: 99%

“…Very large scale integration (VLSI) of the front-end electronics, consisting of preamplifier and associated analog/digital pulse processing, is needed to achieve the required channel density of the newer PET and PET/CT systems, designed to reach millimeter spatial resolution. An integrated CMOS charge-sensitive preamplifier was recently developed and evaluated for the application with APD phoswich detectors [3], [4].…”

Section: Introductionmentioning

confidence: 99%

Design of a fast shaping amplifier for PET/CT APD detectors with depth-of-interaction

Pratte¹,

Pepin²,

Rouleau³

et al.

2001 IEEE Nuclear Science Symposium Conference Record (Cat. No.01CH37310)

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An integrated, 0.35µm CMOS fast shaping amplifier has been designed for coincidence detection and zerocross time pulse shape discrimination (PSD) in PET, and for high rate event counting in CT with APD-based detectors. Analytical simulations of CR-RC n filters of various order and shaping time constant were carried out to optimize the timing performance, keeping in mind the stringent channel density requirements of the detector front-end electronics. The filter was implemented with the biquadratic bandpass architecture using a folded cascode transconductance amplifier. The electronic timing resolution of the coincidence circuit was 92ps in the ideal case without an APD (Cin = 0pF ), and 243ps with an APD (Cin = 30pF ). By comparison, the same system with the CMOS shaper replaced by an Ortec 579 Fast Filter Amplifier set to a shaping time of 10ns yielded an electronic time resolution of 79ps in the ideal case without capacitance, and 236ps with the APD. The 511keV coincidence time resolution for an LSO/APD detector was measured to be 1.49ns.

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A power-efficient, low-noise, wideband, integrated CMOS preamplifier for LSO/APD PET systems

Cited by 53 publications

References 22 publications

Integrated low-noise low-power fast charge-sensitive preamplifier for avalanche photodiodes in JFET-CMOS technology

Integrated low-noise low-power fast charge-sensitive preamplifier for avalanche photodiodes in JFET-CMOS technology

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

Design of a fast shaping amplifier for PET/CT APD detectors with depth-of-interaction

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