Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

Abstract

This paper describes a methodology for selecting drain current, inversion level (represented by inversion coefficient), and channel length for optimum performance tradeoffs in analog CMOS design. Here, inversion coefficient replaces width as a design choice to permit a conscious optimization of inversion level while width is implicitly considered. Transconductance, gate-referred thermal-noise voltage, and drain-source saturation voltage are optimized towards weak inversion while transconductance linearity and drain-referred thermal-noise current are optimized in strong inversion. Voltage gain, flicker noise, and dc mismatch are optimized towards weak inversion at long channel length while bandwidth is optimized in strong inversion at short channel length. Optimization expressions are given along with measured transconductance efficiency and Early voltage from weak through strong inversion over a wide range of channel lengths. Transconductance efficiency and Early voltage are used as normalized measures of transconductance and drain-source resistance, independent of drain current. The methodology presented is used to design three 0.5-µm operational transconductance amplifiers having equal 50-µA bias currents, but different tradeoffs in gain, bandwidth, noise, and dc mismatch. The amplifiers have measured voltage gains of 16.8, 110, and 326 V/V, −3-dB bandwidths of 350, 51, and 5 MHz, input-referred flicker-noise voltage at 100 Hz of 2,000, 450, and 58 nV/Hz 1/2 , and input-referred dc mismatch voltages of 10.2, 2.2, and 1.1 mV respectively. The design methodology can be readily extended to deeper submicron CMOS processes.

Comparative analysis of information rates of simple amplifier topologies

“…One method of characterizing the amplifier design space is to consider performance as a function of the independent variables transistor length and inversion coefficient, which tracks the operation of the transistor from weak to strong inversion [9]. The inversion coefficient can be written…”

Optimizing power-area for constant input-referred noise level in MOSFETs

“…7 If IC>10, the device operates in strong inversion region and if IC<0.1, the device operates in the weak inversion region. If 0.1<IC<10, the device operates in the moderate inversion.…”

“…γ is approximately equal to 1 in PMOS transistor. There are few papers in optimizing power and area for operational amplifiers but these papers present tradeoffs and do not propose a systematic solution for choosing currents and size of the transistors [6]- [7]. This paper organized as follows, in section II optimization of the power and area for one MOSFET is described, while the results and simulations is explained and summarized in section III, finally conclusion are drawn in section IV.…”

Design of a 75‐nW, 0.5‐V subthreshold complementary metal–oxide–semiconductor operational amplifier

“…The low current values allowed by the subthreshold design strategies could be seen as a speed-limiting factor in the op-amp design field. Although the subthreshold regime is well known in the field of circuit design since the 1970s [16], with the widespread diffusion of ultra low-power portable systems, it is particularly gaining attention [10], [12], [17][18][19] to implement ultra low-voltage sub-1-mW amplifiers characterized by larger output swing and lower bias current with respect to traditional amplifiers working in strong inversion region. Moreover, considering the nature of physiological signals, such as the ones involved in the electrooculography, electroencephalography, electrocardiogram, or electromyography, the analog front end of recent biomedical sensors must be able to process signals with amplitudes ranging from a few volts to tens of microvolts and with frequencies span from DC to a few kilohertz [15].…”