A Pipelined Noise-Shaping SAR ADC Using Ring Amplifier

Abstract

In this study, a pipelined noise-shaping successive-approximation register analog-to-digital converter (PLNS-SAR ADC) structure was proposed to achieve high resolution and to be free from comparator design requirements. The inter-stage amplifier and integrator of the PLNS-SAR ADC were implemented through a ring amplifier with high gain and speed. The ring amplifier was designed to improve power efficiency and be tolerant to process–voltage–temperature (PVT) variation, and uses a single loop common-mode feedback (CMFB) circuit. By processing residual signals with a single ring amplifier, power efficiency can be maximized, and a low-power system with 30% lower power consumption than that of a conventional PLNS-SAR ADC is implemented. With a high-gain ring amplifier, noise leakage is greatly suppressed, and a structure can be implemented that is tolerant of mismatches between the analog loop and digital correction filters. The measured signal to noise distortion ratio (SNDR) is 70 dB for a 5.15 MHz bandwidth (BW) at a 72 MS/s sampling rate (Fs) with an oversampling ratio (OSR) of 7, and the power consumption is 2.4 mW. The (= SNDR + BW/Power) is 163.5 dB. The proposed structure in this study can achieve high resolution and wide BW with good power efficiency, without a filter calibration process, through the use of a ring amplifier in the PLNS-SAR ADC.

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

“…More importantly, ringamps are more suitable for fine CMOS processes and have application scenarios in various types of ADCs due to the versatility of their structures. In the last decade, many ringamp-based ADC works [24,[29][30][31][32][33][34][35][36][37][38][39] have appeared. Essentially, there are two different directions of the application, one for high resolution (signal-to-noise-and-distortion-ratio (SNDR) ≥ 70 dB) and the other for high speed (sampling rate fs ≥ 500 MHz), such as the dual-deadzone RAMP-based two-step SAR ADC [34], which achieves the highest SNDR for a ringampbased high-resolution ADC, while [33] used a dead zone degeneration technique to realize the fastest sampling rate (fs = 1 GHz) for single-channel implementation.…”

2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure

“…The use of operational amplifiers in pipelined NS-SAR ADCs is undesirable because operational amplifiers with wide bandwidth eventually require more power consumption. As an alternative, a pipelined NS-SAR ADC using a ring amplifier was proposed in [4]. Due to its inverter-based operation, the ring amplifier is a structure that can satisfy both low power consumption and high operating speed.…”

“…Due to its inverter-based operation, the ring amplifier is a structure that can satisfy both low power consumption and high operating speed. As a result, [4] achieved less power consumption with the same third-order structure to [3] by replacing the amplifier. Although reducing the power consumption, [4] required multi-input comparators for residue voltage summation because the conventional cascaded integrator feed-forward (CIFF) structure was applied.…”

“…As a result, [4] achieved less power consumption with the same third-order structure to [3] by replacing the amplifier. Although reducing the power consumption, [4] required multi-input comparators for residue voltage summation because the conventional cascaded integrator feed-forward (CIFF) structure was applied. The additional input pair of comparator causes additional noise and mismatches, thus deteriorating the performance of NS-SAR ADC.…”

“…The additional input pair of comparator causes additional noise and mismatches, thus deteriorating the performance of NS-SAR ADC. In practice, [4] was implemented as a structure with a third-order NTF. However, it had a somewhat lower SNDR.…”