2nd-Order Pipelined Noise-Shaping SAR ADC Using Error-Feedback Structure

Abstract

This paper presents a pipelined noise-shaping SAR (PLNS-SAR) ADC for high SNDR, wide bandwidth, and low power consumption. The proposed design achieves a sharp second-order NTF of an error feedback structure, without a multi-input comparator and additional residue amplifier. Additionally, the SNDR is improved via zero optimization. Additionally, the speed is enhanced via prediction logic and alternately using the passive switched capacitor FIR filter. This consequently achieves the high-power efficiency of the ADC. The simulated SNDR is 79.97 dB; it achieves a 12.5-MHz BW at a 175-MHz sampling rate, with OSR of 7. The total power consumption of the ADC is 4.27 mW at a 1.1-V supply. The is 174.6 dB. The proposed structure achieves high resolution and wide bandwidth with good energy efficiency.

A 78 dB 0.417 mW Second-Order NS SAR ADC with Dynamic Amplifier-Assisted Integrator

“…This instability of the zero pole in the NTF severely impacts the noise-shaping effect of the system. To address this issue, an additional dynamic amplifier gain calibration circuit needs to be incorporated [9,10]. However, this addition increases the overall circuit's power consumption and subsequently lowers its energy efficiency and figures of merit (FoMs).…”

A Reconfigurable Hybrid ADC Using a Jump Search Algorithm

“…Among recently researched ADCs [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20], various hybrid structures [11][12][13][14][15][16][17][18][19] are being explored. However, the SAR ADC architecture is required due to the low power consumption, bandwidth, and resolution for biomedical signal processing.…”