A physical compact model for direct tunneling from NMOS inversion layers

Clerc, R.; O'Sullivan, P.; McCarthy, K.G.; Ghibaudo, G.; Pananakakis, G.; Mathewson, A.

doi:10.1016/s0038-1101(01)00220-9

Cited by 29 publications

(13 citation statements)

References 24 publications

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“…However, QM analysis shows a significant increase in  S with change in gate voltage in strong inversion [20,21,[78][79][80] and in accumulation regions [25,35,81]. Because of this increase in  S in the inversion and accumulation regions of operation, the QM surface potential  S QM needed for a given population of electrons in the conduction band is higher than the classical surface potential  S cl .…”

Section: Surface Potential Calculation Considering Quantum Mechanicalmentioning

confidence: 99%

Quantum Mechanical Effects in Bulk MOSFETs from a Compact Modeling Perspective: A Review

Srikantaiah

DasGupta

2012

IETE Tech Rev

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In this paper, the quantum mechanical (QM) effects in bulk MOSFETs and their modeling approaches in the compact modeling framework are reviewed. As the device dimensions are scaled to the sub-100 nm range, QM effects affect the device properties, such as effective oxide thickness, inversion layer charge density and profile, threshold voltage, effective bandgap, gate capacitance, mobility, surface potential, subthreshold characteristics, drain current, and gate leakage current. The classical theory is no longer sufficient for accurate modeling of these device characteristics. In this paper, models which have incorporated QM effects to obtain the device characteristics are discussed and compared. The roles of QM effects in affecting some of the device properties are also presented. KeywordsBulk MOSFETs, Quantum mechanical effect, Review on compact modeling. ( ) , which is used to solve eqn. (1) by numerical methods. Only certain energy levels, denoted by E ij , satisfy the Schrödinger equation and correspond to the energy levels of the sub-bands. Here, i=L for the lower valley and i=H for the higher valley, while j=0, 1, 2, 3…, corresponds the sub-band number. The electron concentration n y IETE TECHNICAL REVIEW | VOL 29 | ISSUE 1 | JAN-FEB 2012 AUTHORS Jayadeva Gowrapura Srikantaiah received the B.E. degree in electronics and communication engineering from NMAM Institute of Technology, Nitte, in 1990, M.Tech degree in digital electronics and advanced communication from the Karnataka Regional Engineering College, Surathkal (Present NITK), in 1995, both were affiliated to Mangalore University, India and Ph.D degree from I.I.T. Madras in 2010. His Ph.D. dissertation was on analytical models incorporating quantum mechanical effects for short n-channel MOSFETS. He joined as a lecturer in NMAM Institute of Technology, Nitte, in 1990 and later as Assistant Professor at JNNCE Shimoga in 1998. He has been a Faculty member in the department of electronics and communication engineering, Nagarjuna College of Engineering and Technology, Bangalore, since September 2010 and is currently a Professor and Head. His research interests are modeling and simulation of bulk and SOI MOSFETs including quantum mechanical effects and low power VLSI design.

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Section: Surface Potential Calculation Considering Quantum Mechanicalmentioning

confidence: 99%

Quantum Mechanical Effects in Bulk MOSFETs from a Compact Modeling Perspective: A Review

Srikantaiah

DasGupta

2012

IETE Tech Rev

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“…[11][12][13][14][15][16][17][18][19] Three main tunneling components have been observed: electrons tunneling from conduction band (ECB), electrons tunneling from valence band (EVB), and holes tunneling from valence band (HVB), each of which predominates under different MOS bias conditions, semiconductor types, and gate dielectric materials. [11][12][13][14][15][16][17][18][19] Three main tunneling components have been observed: electrons tunneling from conduction band (ECB), electrons tunneling from valence band (EVB), and holes tunneling from valence band (HVB), each of which predominates under different MOS bias conditions, semiconductor types, and gate dielectric materials.…”

Section: Leakage Current Modelingmentioning

confidence: 99%

Contribution of carrier tunneling and gate induced drain leakage effects to the gate and drain currents of fin–shaped field–effect transistors

Garduno

Cerdeira

Estrada

et al. 2011

Journal of Applied Physics

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Articles you may be interested inImproved modeling of gate leakage currents for fin-shaped field-effect transistors J. Appl. Phys. 113, 124507 (2013); 10.1063/1.4795403 Model of random telegraph noise in gate-induced drain leakage current of high-k gate dielectric metal-oxidesemiconductor field-effect transistors Appl. Phys. Lett. 100, 033501 (2012); 10.1063/1.3678023 Analytical approach to integrate the different components of direct tunneling current through ultrathin gate oxides in n-channel metal-oxide-semiconductor field-effect transistors Effects of inelastic scattering on direct tunneling gate leakage current in deep submicron metal-oxide-semiconductor transistors J. Appl. Phys. 92, 937 (2002); 10.1063/1.1486022Modeling of gate-induced drain leakage current in n-type metal-oxide-semiconductor field effect transistorThe contribution of carrier tunneling and gate induced drain leakage (GIDL) effects in the total gate and drain currents of FinFET devices with different dimensions is analyzed. In order to fulfill this task, expressions for the leakage current due to carrier tunneling and GIDL effects at a Metal-Dielectric-Semiconductor structure were established and incorporated in the Symmetric Doped Double-Gate Model (SDDGM) for metal-oxide-semiconductor field-effect transistors (MOSFET). It is shown that both phenomena have to be taken into account for precise modeling of the device in all the operation regions although GIDL current can become predominant in the subthreshold region. The dependence of gate tunneling current in inversion and subthreshold regimes of operation is modeled as function of the applied voltages and transistor physical parameters by using analytical expressions. The present leakage current model is validated by comparing modeled with measured total gate and drain currents for FinFETs with different dimensions.

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“…Furthermore, while breakdowninduced gate permeability was reported to be similar for positively-stressed nMOS and negatively-stressed pMOS devices, direct-tunneling effects impact at a fairly different extent on nMOS and pMOS devices. Since direct tunnel probability exponentially depends on the inverse of the carrier effective mass ðPr tunnel / expðÀ ffiffiffi ffi m p ÞÞ [18], electron-and hole-leakage currents can be quite different. This results in a less severe degradation of ''low'' logic value, while in ''high'' logic value it can reach an appreciable fraction of logic swing value; it also asymmetrically reflects on noise margins.…”

Section: Analysis Of Static Effectsmentioning

confidence: 99%