A parallel pattern mixed-level fault simulator

Hwang, Tyh-Song; Lee, Chung Len; Shen, Wen Zen; Wu, Ching Ping

doi:10.1145/123186.123449

Cited by 6 publications

(1 citation statement)

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“…This paper presents a mixed-level, (i.e., switch-!ev:'_ and gate-level) transition fault simulator incorporating the PPSFP strategy [18]. The mixed-level feature offers this simulator the capability to handle faults at the transistor-level while still preserving the speed advantage for the gate-level simulation.…”

Section: Introductionmentioning

confidence: 99%

MT-SIM a mixed-level transition fault simulator based on parallel patterns

Lee

Shen

et al. 1992

J Electron Test

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This paper describes a mixed level, (i.e., switch-level and gate-level) transition fault simulator based on parallel patterns: MT-SIM. The switch-level allows the simulator to treat faults at the transistor level, while the gate-level conserves the simulation speed and the parallel pattern strategy further enhances the simulation speed for more than one order of magnitude. The simulator is built based on a set of operators which translate the switchlevel signal propagation into Boolean operations and transform the gate-level logic elements into symbolic logic representations. The experimental results of the simulator show that it can exhibit a linear performance for the logic-level simulation if a longer word length is adopted.

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Section: Introductionmentioning

confidence: 99%