Simulation of non-classical faults on the gate level - The fault simulator COMSIM

Mahlstedt, U.; Alt, J.

doi:10.1109/test.1993.470612

Cited by 19 publications

(3 citation statements)

References 25 publications

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“…Although these methods are very fast, their accuracies are not acceptable, because they only analyze the bridge output voltages without carefully considering how the faults propagate [13]. The performance of the switch-level tools such as SWITEST [14] or the analog simulators like SPICE [5] are not always acceptable, especially if large VLSI circuits have to be analyzed [15]. A different family of methods using mixed level or multilevel simulation techniques have been proposed in [16], [17].…”

Section: B Related Workmentioning

confidence: 99%

Application of fuzzy logic in resistive fault modeling and simulation

Nourani

Attarha

Lucas

2002

IEEE Trans. Fuzzy Syst.

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Abstract-Real defects (e.g., resistive stuck at or bridging faults) in the very large-scale integration (VLSI) circuits cause intermediate voltages which cannot be modeled as ideal shorts. In this paper, we first show that the traditional zero-resistance model is not sufficient for fault simulation. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate level. Our method uses Takagi-Sugeno (TS) fuzzy system to accurately model digital VLSI circuits and produces much more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test-pattern statistics for the ISCAS85 benchmarks.Index Terms-Bridging faults, fault simulation, fuzzy logic, Mamdani model, resistive faults, stuck at faults, Takagi-Sugeno (TS) model, test-pattern generation.

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Section: B Related Workmentioning

confidence: 99%

Application of fuzzy logic in resistive fault modeling and simulation

Nourani

Attarha

Lucas

2002

IEEE Trans. Fuzzy Syst.

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“…Although these methods are very fast, their accuracies are not acceptable, because they only analyze the bridge output voltages without carefully considering how the faults propagate [11]. The performance of the switch level tools such as SWITEST [12] or the analog simulators like SPICE [6] are not always acceptable, especially if large VLSI circuits have to be analyzed [13]. A different family of methods using mixed level or multi-level simulation techniques have been proposed in [14] [15].…”

Section: Related Workmentioning

confidence: 99%

Modeling and simulation of real defects using fuzzy logic

Attarha

Nourani

Lucas

2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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Real defects (e.g. stuck-at or bridging faults) in the VLSI circuits cause intermediate voltages and can not be modeled as ideal shorts. In this paper we first show that the traditional zero-resistance model is not sufficient. Then, we present a resistive fault model for real defects and use fuzzy logic techniques for fault simulation and test pattern generation at the gate-level. Our method produces more realistic fault coverage compared to the conventional methods. The experimental results include the fault coverage and test pattern statistics for the ISCAS85 benchmarks.

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“…The corresponding fault models, translating circuit-level into logic-level data, are referred as the test view of the cell. Other authors have proposed fault models for BRI faults between logical nodes [12,[15][16][17][18]. Here, an extension of the biased voting model [12] is proposed.…”

Section: Bridging Faults Modelsmentioning

confidence: 99%

Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

Santos

Teixeira

1999

Proceedings of the Conference on Design, Automation and Test in Europe

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The validation of high-quality tests requires DefectOriented (DO) fault simulation. The purpose of this paper is to propose a methodology for mixed-level DO fault simulation, using HDL. A novel tool, veriDOFS, is introduced. Structural zooming is performed only for the system module in which the faults are injected. Verilog models for bridging and line open defects are proposed for intra-gate and inter-gate faults. Design hierarchy is exploited, by pre-computing a test view of each cell in a library. The good trade-off accuracy / tractability, as well as the computational efficiency of the new tool are demonstrated by means of structural benchmarks up to 100,000 transistors and 300,000 realistic faults.

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Simulation of non-classical faults on the gate level - The fault simulator COMSIM

Cited by 19 publications

References 25 publications

Application of fuzzy logic in resistive fault modeling and simulation

Application of fuzzy logic in resistive fault modeling and simulation

Modeling and simulation of real defects using fuzzy logic

Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

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