Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

Santos, M.B.; Teixeira, J.P.

doi:10.1145/307418.307562

Cited by 19 publications

(5 citation statements)

References 23 publications

(31 reference statements)

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“…Statistical test algorithms do not require any lower-level data beyond the histograms in the HDB. This separation is similar to mixed-level fault simulation approaches from the past [28] (these approaches did not incorporate process-variation data). It is also useful for handling the intellectual-property issues in a distributed design, manufacturing and test flow, as the test pattern generation can be done using the HDB only and no sensitive technology data must be given to the entity in charge of preparing the test sets.…”

Section: Introductionmentioning

confidence: 65%

Variation-aware fault modeling

Hopsch

Becker

Hellebrand

et al. 2011

Sci. China Inf. Sci.

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To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level information beyond the HDB. The generation of the HDB is demonstrated for primitive cells in 45 nm technology. Preprint General Copyright NoticeThis article may be used for research, teaching and private study purposes. Any substantial or systematic reproduction, re-distribution, re-selling, loan or sub-licensing, systematic supply or distribution in any form to anyone is expressly forbidden. This is the author's "personal copy" of the final, accepted version of the paper published by Science China Press and Springer-Verlag Berlin Heidelberg. 1 Fraunhofer IIS/EAS, Dresden D-010169,G e r m a n y 2 University of Freiburg, Freiburg D-79110,G e r m a n y 3 University of Paderborn, Paderborn D-33098,G e r m a n y 4 University of Passau, Passau D-94023,G e r m a n y 5 University of Stuttgart, Stuttgart D-70569,G e r m a n y Received March 21, 2011; accepted June 21, 2011Abstract To achieve a high product quality for nano-scale systems, both realistic defect mechanisms and process variations must be taken into account. While existing approaches for variation-aware digital testing either restrict themselves to special classes of defects or assume given probability distributions to model variabilities, the proposed approach combines defect-oriented testing with statistical library characterization. It uses Monte Carlo simulations at electrical level to extract delay distributions of cells in the presence of defects and for the defect-free case. This allows distinguishing the effects of process variations on the cell delay from defectinduced cell delays under process variations. To provide a suitable interface for test algorithms at higher levels of abstraction, the distributions are represented as histograms and stored in a histogram data base (HDB). Thus, the computationally expensive defect analysis needs to be performed only once as a preprocessing step for library characterization, and statistical test algorithms do not require any low level i...

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Section: Introductionmentioning

confidence: 65%

Variation-aware fault modeling

Hopsch

Becker

Hellebrand

et al. 2011

Sci. China Inf. Sci.

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“…The work in [5] uses event-based mixed-level fault simulation to simulate the effect of manufacturing defects more accurately while maintaining a tolerable simulation time. It presents a set of fault models for CMOS realistic bridging (BRI) and Line-Open (LOP) faults for efficient fault simulation.…”

Section: State-of-the-artmentioning

confidence: 99%

Laser-Induced Fault Simulation

Natale

Flottes

et al. 2013

2013 Euromicro Conference on Digital System Design

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This paper presents a multi-level simulator for laser-induced fault simulation in digital circuits. It automatically performs the simulation of laser-induced faults using layout information and laser spot information in order to locate affected gates and derive fault-models. The paper mainly focuses on multi-level simulation for obtaining high accuracy of the fault simulation at transistor level and high speed for the simulation of the rest of the circuit. This multilevel process allows handling natural and maliciously induced physical phenomenon leading to circuit misbehavior, while dealing with large circuits.

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“…Work in [121] simulates transistor-level defects using SPICE and abstracts the resulting behavior to logic level by using a new algebra. Work in [122,123] uses mixed-level fault simulation to simulate a defect more accurately while maintaining a tolerable simulation speed. Unfortunately, the work in [43,[117][118][119] depends on simulating the entire circuit at the transistor level and therefore is not scalable.…”

Section: Prior Workmentioning

confidence: 99%

“…Unfortunately, the work in [43,[117][118][119] depends on simulating the entire circuit at the transistor level and therefore is not scalable. The work in [121][122][123], while scalable, does not consider layout and therefore sacrifices accuracy. In addition, the variety of defects considered in [121][122][123] is quite limited.…”

Section: Prior Workmentioning

confidence: 99%

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Physically-Aware Analysis of Systematic Defects in Integrated Circuits

Tam¹,

Blanton

2012

IEEE Des. Test. Comput.

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In the integrated circuit (IC) industry, all products must go through three phases before they are available in the market, namely design, manufacturing, and testing. Design, obviously, refers to the process of converting the early concepts of the product into a precise description of its implementation. Manufacturing then uses this description to fabricate the product, where the design is physically materialized onto the silicon wafer and later packaged into the product. If design and manufacturing are perfect, then every fabricated IC is completely functional, thereby obliterating the need for testing. Unfortunately, both design and manufacturing are not ideal; therefore every manufactured IC must be subject to stringent testing procedures to ensure that most bad ICs are identified and prevented from shipping to the end-users.ICs are deemed bad when they contain certain defects that cause the ICs to fail the specifications.Defects are unintended structural and/or material changes of the IC due to design/manufacturing imperfections.These physical changes may alter the electrical characteristics of the circuit, which are sometimes severe enough to lead to a failure (i.e., violation of one or more design specifications). Common defects in IC manufacturing can be caused by contaminations in the process, variations of the process conditions, or simply the difficulty to fabricate certain features of the design. The last issue is the focus of this dissertation. Defects that arise due to certain aspects of the design being sensitive to the manufacturing process with an elevated likelihood of failure are known as systematic defects. This dissertation addresses the issues related to the prevention and identification of systematic defects by analyzing a large amount of manufactured ICs that have failed testing.For systematic-defect prevention, one common approach is to use design-for-manufacturability (DFM) rules to communicate hard-to-manufacture features to designers so that these features can be minimized in the iii design. Obviously, different rules describe different features and thus their violation/adherence will have different impact on the manufacturability of the product. It is therefore desirable to measure the relative importance of the rules and how they affect product yield. To address this issue, a method called RADAR (Rule Assessment of Defect-Affected Regions) has been developed for measuring the effectiveness of DFM rules in preventing systematic defects. RADAR analyzes a large amount of test data of failed ICs to draw statistical conclusion.Taking preventive measures, such as enforcing DFM rules, is necessary to ensure sufficient product yield. Unfortunately, the amount of resource (circuit area, designer's time, etc.) dedicated to DFM can be quite limited. It is therefore impractical to anticipate and prevent every possible hard-to-manufacture design features before the product is manufactured. Thus, systematic defects can still exist. Therefore, a mechanism is required to identify systematic ...

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Defect-oriented mixed-level fault simulation of digital systems-on-a-chip using HDL

Cited by 19 publications

References 23 publications

Variation-aware fault modeling

Variation-aware fault modeling

Laser-Induced Fault Simulation

Physically-Aware Analysis of Systematic Defects in Integrated Circuits

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