MT-SIM a mixed-level transition fault simulator based on parallel patterns

Abstract

This paper describes a mixed level, (i.e., switch-level and gate-level) transition fault simulator based on parallel patterns: MT-SIM. The switch-level allows the simulator to treat faults at the transistor level, while the gate-level conserves the simulation speed and the parallel pattern strategy further enhances the simulation speed for more than one order of magnitude. The simulator is built based on a set of operators which translate the switchlevel signal propagation into Boolean operations and transform the gate-level logic elements into symbolic logic representations. The experimental results of the simulator show that it can exhibit a linear performance for the logic-level simulation if a longer word length is adopted.