A novel SCR ESD protection structure with low-loading and latchup immunity for high-speed I/O pad

This paper aimed at the study of layout dependence on ESD/LU reliabilities in the O.35um 3.3V low-voltage triggered silicon-controlled-rectifier (LVTSCR) DUTs. In this work, the parameter of channel L in an nMOS, the parameter S of an SCR are varied to study the influence on trigger voltage (Vtt), holding voltage (Vh) and secondary breakdown current (112), Eventually, it can be concluded that the layout illustration of type-2 has a higher 112 than that of type-I, i.e., the ratio of (ldtype-2/(ldtype-1 > 1.3 among all the LVTnSCRs. Meanwhile, the holding voltages of SCR devices are latch-up (LU) free while operated at 3.3V.Therefore, the type-2 layouts of SCR device are so excellent structure in the ESD/LU reliability considerations for power management applications.

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A novel SCR ESD protection structure with low-loading and latchup immunity for high-speed I/O pad

Cited by 6 publications

References 2 publications

Design, fabrication and test of novel LDMOS-SCR for improving holding voltage

Design, fabrication and test of novel LDMOS-SCR for improving holding voltage

The Design of Bi-CMOS LVDS Output Buffer with ESD Protection Circuit Using 90nm CMOS Technology

Layout-type dependence on ESD/LU reliabilities for LVTnSCR devices

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