In this paper, we implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per clock.

No abstract

No abstract

No abstract

No abstract

No abstract

Abstract:In this paper, we have investigated the electrical characteristics of Silicon Controlled Rectifier (SCR)-based ESD power clamp circuit with high holding voltage for whole-chip ESD protection. The proposed ESD power clamp circuit (HHVSCR: High Holding Voltage SCR) has different well (n/p-well) length (3/7 µm -8/2 µm) and p-drift (p+) length (8 µm -16 µm). The measurement results indicate that dimension of n/p-well and p-drift has a great effect on holding voltage (2 V-5 V) and a little effect on the triggering voltage (6.5 V∼7 V). And the whole-chip ESD protection was designed for 2.5∼3.3 V applications, this whole-chip ESD protection design can be discharged in ESD-stress mode (PD, ND, PS, NS) as well as VDD-VSS mode. The robustness of the novel ESD protection cells were measured to 6 kV (HBM: Human Body Model), 280 V (MM: Machine Model).

No abstract