A novel powering-down scheme for low Vt CMOS circuits

Kumagai, K.; Iwaki, Hiroyuki; Yoshida, Hidetaro; Suzuki, Hiroto; Yamada, Takazo; Kurosawa, S.

doi:10.1109/vlsic.1998.687998

Cited by 50 publications

(33 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The low power consumption in CMOS circuits can also effective the reducing capacitance. The effective capacitance is defined by the product of the physical capacitance and the switching activity [5], which is shown as…”

Section: B) Reducing Effective Capacitancementioning

confidence: 99%

“…The tree structures can be applied to implement a circuit with both of the balanced signal paths and less logic depth, while the chain structures are quite the contrary. A good example in Figure 4 illustrates the choice of the tree or chain structures [5]. The second adder computes twice and the third adder computes three times per cycle due to the finite propagation delay through the previous adders.…”

Section: Minimizing Glitching Activitymentioning

confidence: 99%

See 1 more Smart Citation

Ultra-Low Power Designing for CMOS Sequential Circuits

Sreenivasulu¹,

Rao²,

Babu³

2015

IJCNS

View full text Add to dashboard Cite

Power consumption is the bottleneck of system performance. Power reduction has become an important issue in digital circuit design, especially for high performance portable devices (such as cell phones, PDAs, etc.). Many power reduction techniques have also been proposed from the system level down to the circuit level. High-speed computation has thus become the expected norm from the average user, instead of being the province of the few with access to a powerful mainframe. Power must be added to the portable unit, even when power is available in non-portable applications, the issue of low-power design is becoming critical. Thus, it is evident that methodologies for the design of high-throughput, low-power digital systems are needed. Techniques for low-power operation are shown in this paper, which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. The threshold voltages of the MTCMOS devices for both low and high Vth are constructed as the low threshold Vth is approximately 150 -200 mv whereas the high threshold Vth is managed by varying the thickness of the oxide Tox. Hence we are using different threshold voltages with minimum voltages and hence considered this project as ultra-low power designing.

show abstract

Section: B) Reducing Effective Capacitancementioning

confidence: 99%

Section: Minimizing Glitching Activitymentioning

confidence: 99%

Ultra-Low Power Designing for CMOS Sequential Circuits

Sreenivasulu¹,

Rao²,

Babu³

2015

IJCNS

View full text Add to dashboard Cite

show abstract

“…1. Sleep leakage reduction techniques [14], [15]. switch and the wire segment it drives are often referred to as a routing resource.…”

Section: B Fpga Hardware Structuresmentioning

confidence: 99%

Low-Power Programmable FPGA Routing Circuitry

Anderson

Najm

2009

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Abstract-We consider circuit techniques for reducing FPGA power consumption and propose a family of new FPGA routing switch designs that are programmable to operate in three different modes: high-speed, low-power, or sleep. High-speed mode provides similar power and performance to traditional FPGA routing switches. In low-power mode, speed is curtailed in order to reduce power consumption. Leakage is reduced by 28-52% in low-power versus high-speed mode, depending on the particular switch design selected. Dynamic power is reduced by 28-31% in low-power mode. Leakage power in sleep mode, which is suitable for unused routing switches, is 61-79% lower than in high-speed mode. Each of the proposed switch designs has a different power/area/speed trade-off. All of the designs require only minor changes to a traditional routing switch and involve relatively small area overhead, making them easy to incorporate into current commercial FPGAs. The applicability of the new switches is motivated through an analysis of timing slack in industrial FPGA designs. It is observed that a considerable fraction of routing switches may be slowed down (operate in lowpower mode), without impacting overall design performance.

show abstract

“…Power gating is one well-known way of reducing leakage and it continues to be applied to very-deep submicron CMOS technologies. There has been a lot of work on the multi-threshold voltage CMOS (MTCMOS) technique, which uses a MOSFET switch to gate, or cut off, a circuit from its power rail(s) during standby mode [3][4][5][6]. Without a clear understanding of the technique, however, the negative effects of power gating, such as, inductive noise and the range of device options, make it difficult to realize the potential benefits.…”

Section: Introductionmentioning

confidence: 99%

Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

Lee¹,

Lee²,

Woo

et al. 2008

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

Abstract-We present a power gating turn-on mechanism that digitally suppresses ground-bounce noise in ultra-deep submicron technology. Initially, a portion of the sleep transistors are switched on in a pseudorandom manner and then they are all turned on fully when VVDD is above a certain reference voltage. Experimental results from a realistic test circuit designed in 65nm bulk CMOS technology show the potential of our approach.

show abstract

A novel powering-down scheme for low Vt CMOS circuits

Cited by 50 publications

References 3 publications

Ultra-Low Power Designing for CMOS Sequential Circuits

Ultra-Low Power Designing for CMOS Sequential Circuits

Low-Power Programmable FPGA Routing Circuitry

Power-Gating Structure with Virtual Power-Rail Monitoring Mechanism

Contact Info

Product

Resources

About