A novel LTPS-TFT-based charge-trapping memory device with field-enhanced nanowire structure

Drain-induced Schottky barrier source-side hot carriers and its application to program local bits of nanowire charge-trapping memories

“…Nitride hard-mask spacer lithography was employed to fabricate the silicon nanowire without the need of advanced lithography. 19,20,25) The detailed steps to fabricate the Schottky barrier nanowire SONOS cells can be found in. 19,20) To fabricate the poly-Si channel, an amorphous silicon layer is deposited and then transformed by the solid phase crystallization into a poly-Si layer.…”

Schottky Barrier Silicon Nanowire SONOS Memory With Ultralow Programming and Erasing Voltages

“…The adoption of silicon gate-all-around nanowire in SONOS memory improves programming and erasing considerably. The enhancement of the local electric field in the nanowire SONOS cell is attributed mainly to the use of a smaller diameter [1]- [5] or shaper corners [6], [7] of silicon nanowire. However, a high gate voltage of 10-17 V is still required for cell programming or erasing.…”

“…S ILICON nanowire has attracted growing interest from the semiconductor industry to replace the bulk silicon-oxidenitride-oxide-silicon (SONOS) memory in future cell scaling [1]- [3], system-on-chip [4], [5], system-on-panel [4], [6], [7], and 3-D integration [8] applications. The adoption of silicon gate-all-around nanowire in SONOS memory improves programming and erasing considerably.…”

“…Results from two state-of-the-art nonsilicidation counterparts[6],[7] are indicated for comparison. source/drain silicidation.…”

“…Results from two state-of-the-art counterparts[6],[7] are indicated for comparison, while those nanowire cells are fabricated without 0741-3106/$26.00 © 2011 IEEE…”