A study on poly-Si thin-film transistor (TFT) SONOS memory cells with source/drain engineering

Tsui, Bing‐Yue; Lai, J.M.

doi:10.1109/essderc.2011.6044200

Cited by 1 publication

(1 citation statement)

References 16 publications

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“…In our FeTFTs, the formation of an interfacial layer can be suppressed by using an oxide semiconductor channel; the absence of an interfacial layer yielded stable endurance characteristics. In addition, a comparison was made between this work and previous memory devices such as charge-trap memory, perovskite oxide-based ferroelectric transistors, and hafnia-based ferroelectric transistors (table S1) (12,23,29,31,(45)(46)(47)(48)(49)(50)(51). The use of HfZrO x and InZnO x resulted in lower operation voltage, faster operation speed, and lower processing temperature compared to conventional charge-trap memory and perovskite oxide-based ferroelectric transistor.…”

Section: Combination Of Hafnia-based Ferroelectrics and Oxide Semicon...mentioning

confidence: 97%

CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

2021

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Ferroelectric memory has been substantially researched for several decades as its potential to obtain higher speed, lower power consumption, and longer endurance compared to conventional flash memory. Despite great deal of effort to develop ferroelectric memory based on perovskite oxides on Si, formation of unwanted interfacial layer substantially compromises the performance of the ferroelectric memory. Furthermore, three-dimensional (3D) integration has been unimaginable because of high processing temperature, non-CMOS compatibility, difficulty in scaling, and complex compositions of perovskite oxides. Here, we demonstrate a unique strategy to tackle critical issues by applying hafnia-based ferroelectrics and oxide semiconductors. Thus, it is possible to avoid the formation of interfacial layer that finally allows unprecedented Si-free 3D integration of ferroelectric memory. This strategy yields memory performance that could be achieved neither by the conventional flash memory nor by the previous perovskite ferroelectric memories. Device simulation confirms that this strategy can realize ultrahigh-density 3D memory integration.

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Section: Combination Of Hafnia-based Ferroelectrics and Oxide Semicon...mentioning

confidence: 97%

CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

2021

View full text Add to dashboard Cite

show abstract

A study on poly-Si thin-film transistor (TFT) SONOS memory cells with source/drain engineering

Cited by 1 publication

References 16 publications

CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

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