CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory

Abstract

Ferroelectric memory has been substantially researched for several decades as its potential to obtain higher speed, lower power consumption, and longer endurance compared to conventional flash memory. Despite great deal of effort to develop ferroelectric memory based on perovskite oxides on Si, formation of unwanted interfacial layer substantially compromises the performance of the ferroelectric memory. Furthermore, three-dimensional (3D) integration has been unimaginable because of high processing temperature, non-CMOS compatibility, difficulty in scaling, and complex compositions of perovskite oxides. Here, we demonstrate a unique strategy to tackle critical issues by applying hafnia-based ferroelectrics and oxide semiconductors. Thus, it is possible to avoid the formation of interfacial layer that finally allows unprecedented Si-free 3D integration of ferroelectric memory. This strategy yields memory performance that could be achieved neither by the conventional flash memory nor by the previous perovskite ferroelectric memories. Device simulation confirms that this strategy can realize ultrahigh-density 3D memory integration.

Ferroelectric HfO2 Memory Transistors With High-κ Interfacial Layer and Write Endurance Exceeding 1010 Cycles

“…by using a non-Si channel ( [22], [23]). However, FeFET endurance on crystalline Si is still limited to 10 4 -10 6 cycles.…”

CMOS-compatible compute-in-memory accelerators based on integrated ferroelectric synaptic arrays for convolution neural networks

“…1C). The program-inhibit voltage reduces the difference between the voltages of the GL and the channel layer of the unselected FeTFT, and this can prevent polarization switching in the unselected devices ( 43 ). After the parallel programming operation, the states of the devices in the same column could be confirmed simultaneously by measuring the current of the DLs, while a read voltage of 0.1 V was applied to the selected SL.…”

Fenton Reaction for Enhancing Polishing Rate and Protonated Amine Functional Group Polymer for Inhibiting Corrosion in Ge1Sb4Te5 Film Surface Chemical-Mechanical-Planarization

“…Recently, memory semiconductor device technologies have evolved to achieve fast switching, low-power consumption, and low memory bit-cost via the scaling-down of memory cells. Thus, two types of memory devices have been classified in terms of switching speed, power consumption, and cost per bit: dynamic random-access memory (DRAM) and three-dimensional (3D) NAND flash memory [1][2][3]. However, a 3D cross-point memory using phase-change random-access memory (PCRAM) has been proposed to generate a new storage memory in the memory hierarchy.…”