A novel low-power FPGA routing switch

Anderson, Jason; Najm, Farid N.

doi:10.1109/cicc.2004.1358930

Cited by 31 publications

(17 citation statements)

References 18 publications

(25 reference statements)

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“…In [75] , the author introduced the energyefficient modules for embedded components in FPGAs to reduce power by optimizing the number of connections between the module and the routing resources, and by using reduced supply voltage circuit techniques. A novel FPGA routing switch with high-speed, low-power, or sleep modes have been presented in [76] . The switch reduces dynamic power for non timing critical logic and standby power for logic when it is not being used.…”

Section: Power Reduction At Architecture-and Circuitlevel Designmentioning

confidence: 99%

Reduction of Power Consumption in FPGAs - An Overview

Grover¹,

Soni²

2012

IJIEEB

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-Field Programmable Gate Arrays FPGAs are highly desirable for implementation of digital systems due to their flexibility, programmability and low end product life cycle. In more than 20 years since the introduction of FPGA, research and development has produced dramatic improvements in FPGA speed and area efficiency, narrowing the gap between FPGAs and ASICs and making FPGAs the platform of choice for implementing digital circuits. FPGAs hold significant promise as a fast to market replacement. Unfortunately, the advantages of FPGAs are offset in many cases by their high power consumption and area. The goal is to reduce the power consumption without sacrificing much performance or incurring a large chip area so that the territories of FPGAs applications can expand more effectively. Reducing the power of FPGAs is the key to lowering packaging and cooling costs, improving device reliability, and opening the door to new markets such as mobile electronics. This paper presents the tips to lower down the static and dynamic power dissipation in FPGAs. It gives an overview of various techniques at system, device, and circuit and architecture level used for reduction of power consumption of FPGAs and their outcomes.

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Section: Power Reduction At Architecture-and Circuitlevel Designmentioning

confidence: 99%

Reduction of Power Consumption in FPGAs - An Overview

Grover¹,

Soni²

2012

IJIEEB

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“…A V DD -selection approach for routing buffers which does not have this limitation [29] appears in Figure 5.17. This work proposes a new switch architecture which adds two transistors, MNX and MPX, to the buffer in the routing switch (this differs from [137] which used two PMOS devices connected to two different power rails).…”

Section: Power Related Issuesmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

318

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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“…Anderson et al [65] have presented a novel FPGA routing switch design to reduce the leakage and dynamic power consumption. The switch can be programmed to operate in any one of the mode: high speed, low speed, or sleep mode.…”

Section: Field -Programmable Gate Arraymentioning

confidence: 99%

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

Singh¹

2017

Field - Programmable Gate Array

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The design of low-power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low-power SRAMbased FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data-aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power-efficient SRAM-based FPGA.

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A novel low-power FPGA routing switch

Cited by 31 publications

References 18 publications

Reduction of Power Consumption in FPGAs - An Overview

Reduction of Power Consumption in FPGAs - An Overview

FPGA Architecture: Survey and Challenges

Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture

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