A Novel Isolation Method for Half-Bridge Power ICs

Kong, Moufu; Chen, Xingbi

doi:10.1109/ted.2013.2263578

Cited by 6 publications

(4 citation statements)

References 11 publications

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“…Our proposed device structure has been designed using the high-voltage isolation process based on a self-isolation technique. [1][2][3][4][5] The self-isolation technique is more cost effective than the junction isolation [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22] and dielectric isolation techniques. [23][24][25][26][27][28][29][30] This is because it uses a lessexpensive silicon wafer that is uniformly doped, and it does not need special process steps such as deep diffusion layer and trench formations for the isolation process.…”

Section: Device Conceptmentioning

confidence: 99%

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

Yamaji

Jonishi

Sumida

et al. 2015

Jpn. J. Appl. Phys.

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A new 800 V-class lateral high-voltage n-channel MOS (HVNMOS) structure with a markedly reduced parasitic capacitance (C oss ) has been developed for integration in a high-voltage gate driver IC. In our new HVNMOS, a 40% C oss reduction from that of a conventional HVNMOS can be achieved by using two n-type drift regions divided by a p-type diffusion layer. We have confirmed that a 12% shorter I/O propagation delay time can be achieved by using the new HVNMOS of the high-voltage IC (HVIC) test chip. In this paper, the design concept of the developed HVNMOS is presented with the simulation and experimental results.

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Section: Device Conceptmentioning

confidence: 99%

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

Yamaji

Jonishi

Sumida

et al. 2015

Jpn. J. Appl. Phys.

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“…6 b as that of n ‐LDMOS M L . Hence the total effective charge density of surface voltage sustaining areas of isolation area in the X ‐direction requires to meet the effective surface charge density distribution of the n ‐LDMOS M L ’s [18, 19]. In other words, the total effective surface donor flux density of the isolation area at the surface in X ‐direction must be almost the same as that of the M L ’s.…”

Section: Structure Of Generating Two Control Voltages For Turn‐on Amentioning

confidence: 99%

“…For simplify the process of implementation, note that only a change of the dose of the p ‐region can achieve the demand of effective surface charge distribution of the isolation area [19]. Fig.…”

Section: Structure Of Generating Two Control Voltages For Turn‐on Amentioning

confidence: 99%

Novel technique for lateral high‐voltage totem‐pole power devices

Kong

Chen

2014

IET Power Electronics

Self Cite

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A novel technique and related structure for a high-voltage integrated circuit (IC) with totem-pole high-voltage devices are proposed. In this technique, a low control voltage with respect to the tub is used to drive the high-side device in the totem pole through a low-voltage tub circuit, as well as through very small low-side device to drive a low-voltage ground circuit, which in turn drives the low-side device in the totem pole. Therefore, the high-voltage level-shifting circuit can be replaced by the tub circuit which takes only a very small area and has no parasitic effects in comparison with that in the conventional totem-pole high-voltage IC. The structure of low-voltage power supplies for low-voltage ICs is also proposed. The results of numerical simulation verify the applicability of the proposed structure.

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“…In a silicon-based LDMOS device, the concept of optimum variation lateral doping (OPT-VLD) is widely used to improve and optimize the trade-off relationship between BV and R on,sp in LDMOS devices. Since the diffusion coefficient of impurities in the Si material is relatively large, the entire OPT-VLD region can be realized by the same ion implantation process [29][30][31]. However, due to the extremely low diffusion coefficient of impurities in SiC, realization of the VLD region has become a challenge, and a SiC LDMOS based on VLD technology has not been well established [21,32].…”

Section: Introductionmentioning

confidence: 99%

A novel optimum variation lateral doping SiC lateral double-diffused metal oxide semiconductor with improved performance

Kong¹,

Duan²,

Gao³

et al. 2022

Semicond. Sci. Technol.

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A novel optimum variation lateral doping 4H-SiC lateral double-diffused metal-oxide- semiconductor field-effect transistor (LDMOS) with improved performance is proposed and numerical simulation investigated in this article. As for the proposed 4H-SiC LDMOS, an optimized three-stage variation of lateral doping (VLD) p-top layer is employed in the drift region, thus the doping concentration of the n-drift region can be significant increased, resulting an ultra-low specific resistance (Ron,sp). The breakdown voltage (BV) is also improved, since the electric field distribution of the drift region is optimized. Besides, the current saturation characteristic, gate-drain capacitance (CGD) and gate-to-drain charge (Qgd) of the proposed device are all improved, thanks to the effect of the source connected p-top region. Compared with the conventional LDMOS, the numerical simulation results show that the BV, Ron,sp and Qgd of the proposed LDMOS are improved by more than 11.9%, 47.3% and 46.3%, respectively. And the three-dimensional simulation result indicates that the entire three-stage p-top VLD layer can be performed by one-time fabrication process, which brings great convenience to future production.

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A Novel Isolation Method for Half-Bridge Power ICs

Cited by 6 publications

References 11 publications

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

Proposal of a new lateral high-voltage n-channel MOS structure with a reduced parasitic output capacitance for a level-shift circuit integrated in 800 V-class high-voltage ICs

Novel technique for lateral high‐voltage totem‐pole power devices

A novel optimum variation lateral doping SiC lateral double-diffused metal oxide semiconductor with improved performance

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