A novel energy efficient voltage level shifter

Machiraju, Pavan Kumar; Pushpamithra, D. Y.

doi:10.1109/icsemr.2014.7043658

Cited by 7 publications

(4 citation statements)

References 13 publications

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“…To verify the performance of the modified voltage level shifter for multiscaling, the reported EVLS has been implemented using 90 nm CMOS technology and simulated at the frequency of 5 MHz on Cadence Virtuoso tool. The simulated wave for the EVLS (Machiraju and Pushpamithra, 2014) for up and down voltage conversion is shown in Figures 9 and 10, respectively. The simulated waveforms for up conversion and down conversion of modified voltage level shifter with the similar inputs and conditions as EVLS are presented in Figures 11 and 12.…”

Section: Resultsmentioning

confidence: 99%

“…EVLS (Machiraju and Pushpamithra, 2014;da Rocha et al, 2008), as shown in Figure 7, consists of two parts: Vddl and Vddh, which is chosen depending upon the input voltage Vin that is realized by transistors Q1 and Q2 and level shifting, which is done by the remaining part of the circuit. Transistor Q1 is turned ON whenever Vin is at 1.2V and at the same time transistor Q2 is turned OFF, as a result of which Vdd sets to Vddh.…”

Section: Energy Efficient Voltage Level Shiftermentioning

confidence: 99%

“…Bootstrapping generic voltage level shifter is proposed by Vaidya et al (2018). In 2014, Machiraju and Pushpamithra (2014) proposed the energy-efficient voltage level shifter (EVLS) circuits, which require only ten transistors and provide low power dissipation and low delay. Two level shifters are proposed by Tran et al (2005), which are suitable for block-level dynamic voltage scaling environments.…”

Section: Introductionmentioning

confidence: 99%

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Performance analysis of multi-scaling voltage level shifter for low-power applications

Vaithiyanathan

Kurmi

Mishra

et al. 2020

WJE

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Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

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Section: Resultsmentioning

confidence: 99%

Section: Energy Efficient Voltage Level Shiftermentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Performance analysis of multi-scaling voltage level shifter for low-power applications

Vaithiyanathan

Kurmi

Mishra

et al. 2020

WJE

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“…CMOS technology is being widely used to meet the increasing demand for low power consumption and low delay operation in microelectronics circuit systems [2] [3]. Considerable reduction in chip size (<1 mm 2 ) has become possible with the advancement of CMOS technology which minimizes the manufacturing cost greatly.…”

Section: Introductionmentioning

confidence: 99%

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Badal¹,

Reaz²,

Farayez³

et al. 2017

JESTR

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Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 µm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 µm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.

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