An automated smart home system is a key contributor to user assistance technology in modern civilization. Crucial merit of such a system is its ability to train itself through recorded data and recognize patterns in resident behaviors. Lack of sufficient prediction accuracy, exponential memory consumption, and extensive runtime prevent many of the current activity prediction approaches from being seamlessly integrated into consumer residences. This research introduces a sequence prediction algorithm which uses a prefix tree-based data model in order to learn and predict user actions. The algorithm applies episode discovery to detect correlated sensor events and learns the activities using a lossless data compression technique. This process assigns a probability of occurrence to sensor events and uses these probabilities to detect patterns in resident behavior. A complexity analysis of the algorithm is done to prove its efficiency in terms of memory usage and runtime. Using the presented technique, predictions are performed on popular datasets and contrasted with existing algorithms. The proposed algorithm achieves an 8.22% improvement in prediction accuracy over its predecessors, along with 66.69% better memory efficiency and 37% faster runtime.
Smart home or home automation has become widely popular especially in the case of easing the lives of people with special needs, for instance the elderly and handicapped people. In every home, a specific user has a unique pattern or sequence of using the functions of that house. Recognizing that unique pattern is the key to ensuring an intelligently and properly automated household where the house will remember the behavior of a user and predict the next service required by the user successfully. In this research, a recently developed algorithm named as sequence prediction via enhanced episode discovery (SPEED) is considered for modification by inclusion of location agents. A smart home prototype consisting of two rooms is designed as a testbed for verification. The results show that the accuracy of this algorithm is more than 40%, which is better than the previous SPEED. Moreover, the algorithm detects the location of next predicted event. Since human activity can be distinguished by their existing locations, predicting the next event as well as the location helps to determine the next action more accurately.
Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 µm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 µm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.
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