A novel E-mode GaN p-MOSFET featuring charge storage layer with high current density

Abstract

In this work, a trench gate enhancement-mode (E-mode) GaN p-type Metal Oxide Semiconductor Field Effect Transistor featuring charge storage layer is proposed, which exhibits an effectively improved current density. Compared with conventional devices without charge storage layer, the current density can be increased by 154% (@VDS=-5V, VGS=-7V). Besides, the simulation has been conducted to obtain the optimized AlGaN barrier thickness t, Al mole-fraction x, trench gate depth Trecess, and negative charge concentration NCSL. In this case, the p-MOSFETs show an on-current |ION, max| of 14 mA/mm, VTH of -0.47 V, ION/IOFF of >108, and on-resistance RON of 0.27 kΩ.mm. The proposed GaN p-MOSFETs exhibit a promising method to improve the current drive capability of GaN p-channel devices.

Special issue on wide-bandgap semiconductors and applications

“…They are essentially suitable for various applications targeting low losses and high operating frequencies and temperatures. This special issue evaluates a series of GaN-and AlGaN-based electronic devices proposed by Chinese researchers, such as Schottky barrier diodes (SBDs) [19], metal-oxide-semiconductor field effect transistors (MOSFETs) [20], high electron mobility transistors (HEMTs) [21][22][23][24][25], and so forth.…”

“…The inclusion of graphene increased the Schottky barrier height from 1.194 eV to 1.443 eV, as determined by the thermionic emission model and barrier inhomogeneity model. By using the p-GaN/AlGaN/GaN double-heterojunction, Chen et al [20] designed a trench gate enhancement-mode p-MOSFET featuring a charge storage layer, and the simulation results exhibit an enhancement of 154% of current density compared with conventional devices. The study shows a potential method of improving the current conduction capability of GaN p-channel devices, which are suitable for GaN monolithic integration.…”

Highly Scaled GaN Complementary Technology on a Silicon Substrate

“…While each approach has its own merits, the next chapter of GaN CT research should adopt an application-driven perspective, where stringent requirements should be placed on: 1) easy integration of p-FETs and n-FETs on the same platform, ideally, without the need of regrowth steps that increase cost; 2) scalable platform to accelerate commercialization; 3) ability to withstand the large heat generation in EVs, data centers, and base stations; and 4) most importantly, concurrently high performance of both p-FET and n-FET. Thus far, discrete GaN p-FETs have received significant attention [13], [14], [15], [16], [17], [18], [19], [20], [21], but equal attention should be paid to their monolithic integration with n-FETs.…”