A novel differential XOR-based self-checking adder

An Efficient Differential Full Adder

“…The differential XOR gate [20]. the inputs of the second differential XOR that generates the dual sum function as shown in Fig. This differential XOR is shown in Fig 6. This fully differential implementation requires only 28 transistors.…”

“…Table 2 summarizes the overhead for each type of adder. The Layout of the CMOS full adder and the Layout full adder in combined technology [20] are shown respectively in Fig. 11 and Fig.…”

Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” [Dec 07 2696-2705]

“…INTRODUCTION: Self-checking carry-select adder (CSeA) with reduced area overhead was presented by Vasudevan et al [1]. The proposed design seemed to be promising for self-checking CSeA, and therefore, the work was referred to for comparison by Alioto et al [2], Belgacem et al [3] and Wang et al [4]. However, we find that the claim for self-checking is only valid for 2-bit CSeA, and the 6-bit CSeA shown in the paper cannot provide self-checking.…”