Comments on “Self-Checking Carry-Select Adder Design Based on Two-Rail Encoding” [Dec 07 2696-2705]

Abstract

We first show that self-checking presented in the above paper does not work for carry-select adder with input bits higher than 2. Then, we present a correct design and show that the resulting overhead almost doubles.

Enhanced Self Checking Carry Select Adder using Dynamic Logic Based Full Adder

“…With this inclusion they claimed that, their design was totally self checking. But authors showed and proved that it does not work for CSLA with input bits higher than 2 [2]. To overcome the difficulty, they [2] modified the structure given by [1] by introducing an AND logic (ref.…”

“…The implementation of quicker, more precise and area efficient adders are of high concern in those systems. Self checking facility had been included and a new scheme to encode the addition bits using two rail codes is proposed [2]. Each one of the adders which have been designed over the years has different trade-offs as shown in [3].…”

“…Here again satisfactory results were not met and it was also not having self checking multiplexers and de-multiplexers. This paper proposes a modification to the circuits that were used by [1][2] using dynamic logic instead of a regular CMOS logic. It uses only ten transistors for constructing the full adder section.…”

“…It also introduces a three transistor X-NOR circuit which will replace the existing X-NOR circuit. No changes have been made to two pair two rail checker, which has been used by [1][2]. Our work is organized as follows.…”

“…Our work is organized as follows. Section 2 presents the faulty design [1] & corrected design of self checking CSLA by [2]. Section 3 illustrates the proposed and modified design of self checking CSLA using dynamic logic.…”