Enhanced Self Checking Carry Select Adder using Dynamic Logic Based Full Adder

Abstract

Fast adders are constructed mainly by Carry select adders (CSLA). Area is one of the main concerns as far as any VLSI design is considered. In connection this paper enhances the performance of self checking carry select adder by introducing un footed dynamic logic based full adder cell instead of a regular CMOS based adders. The adder is constructed with 10 transistors based on the optimization of truth tale of a full adder. A 3 transistor X-NOR gate circuit is also used instead of a conventional X-NOR circuit in the self checking path. Adders of size 4 bit and 8 bit are constructed in various technologies. The results show that the proposed structure reduces the transistor over head by almost 47% and 46% for 4bit and 8bit structures respectively. By achieving this much of reduction in area this work could be suggested for higher order VLSI structures like BIST,DCT etc.,