A Novel Energy-Efficient Hybrid Full Adder Circuit

Sharma, Trapti; Kumre, Laxmi

doi:10.1007/978-981-10-8360-0_10

Cited by 2 publications

(1 citation statement)

References 15 publications

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“…Full output voltage swing and less noise is required for efficient implementation of any digital circuit. GDI (Gate-Diffusion-Input) is another technique in the literature which can provide power and speed efficiency along with full voltage swing at the output [26][27][28][29][30]. Efficiency of GDI technique can be improved by using Mixed Threshold Voltage (MVT) scheme [31].…”

Section: Previous Contributionmentioning

confidence: 99%

Sleepy- Gate Diffusion Input (S-GDI) — Ultra Low Power Technique for Digital Design

Sharma*,

Sohal

2019

IJITEE

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In this paper we propose a power efficient technique called Sleepy- Gate Diffusion Input (S-GDI) that can be used for efficient digital design at nano scale foundries. For area and power comparison, ten prior techniques are taken in to consideration and applied on XOR gate, 1-bit adder, 1-bit comparator and 4- bit up-down counter. All techniques are parametrically analyzed on 65nm technology. The proposed S-GDI technique has been observed power efficient as compared to Complementary CMOS technique (CCT), Complementary Pass Transistor Logic (CPTL), DCMOS (Differential CMOS), Differential Cascode Voltage Switch with Pass Gate Logic (DCVSPG), Energy Economized Pass Transistor Logic (EEPL), Lean Integration with Pass Transistors (LEAP), Push-Pull Pass Transistor Logic (PPL), Pass Transistor Logic (PTL), CMOS with Transmission Gate (TG) and Gate diffusion Input (GDI). As compared to GDI technique S-GDI is showing 96.20%, 93.65%, 97.88% and 98.22% power efficiency for XOR, 1-bit adder, 1-bit comparator and 4-bit up-down counter respectively. S-GDI is showing area efficiency of 17.16% and 28.1% for XOR, 41.26% and 53.89% for 1-bit adder, 7.6% and 21.76% for 1-bit comparator and 6.7% and 28% for up-down counter over EEPL and DCMOS technique respectively. Although other techniques except EEPL and DCMOS techniques are area efficient as compared to proposed technique but this is on the expense of higher total power dissipation. So, PDP (power delay products) of all considered techniques are also calculated on 65nm technology for both SUM and CARRY outputs of 1-bit adder. In both cases power delay product for S-GDI technique is very less as compared to all other considered technique. Due to efficiency of S-GDI in terms of considered parameters, this technique can be efficiently used for low power applications

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