A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops

Estebsari, Motahhareh; Gholami, Mohammad; Ghahramanpour, Mohammad Javad

doi:10.1007/s00034-016-0481-6

Cited by 9 publications

(9 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In reverse, when DOWN signal is high, the charge pump causes capacitor discharge in output node. When both signals are high, the current of the current source is injected into both branches …”

Section: Wide Range Delay Locked Loopmentioning

confidence: 99%

See 1 more Smart Citation

A wide range delay locked loop for low power and low jitter applications

Estebsari

Gholami

Ghahramanpour

2017

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

Summary In this paper, a design of analog delay locked loop is introduced in which new techniques are applied to eventually increase operating frequency range and reduce jitter considerably. In this design, all blocks of a delay locked loop including a voltage controlled delay line, charge pump, and loop filter are accurately designed. A new delay cell is proposed with wide delay range, in which increase of delay range results in using fewer cells, and consequently the power consumption will decrease. Current mirror techniques and feedback in the proposed charge pump also cause higher current matching and better jitter performance. This delay locked loop, which is designed with TSMC 0.18‐μm CMOS technology, has a wide frequency range from 217 to 800 MHz. It consumes maximum 3.4‐mW and minimum 2.6‐mW power dissipation in source voltage of 1.8 V, which is suitable for low power applications. It also has an appropriate lock time that is at least equal to 3 clock cycles at 217 MHz and at most 25 clock cycles at 800 MHz. Jitter performance in this delay locked loop is improved significantly: RMS jitter is 0.65 ps at 800 MHz and 2.54 ps at 217 MHz. Moreover, its maximum peak‐to‐peak jitter is equal to 5.17 ps, and its minimum peak‐to‐peak jitter is equal to 1.39 ps at 217 and 800 MHz, respectively.

show abstract

Section: Wide Range Delay Locked Loopmentioning

confidence: 99%

“…When both signals are high, the current of the current source is injected into both branches. 14 When UP signal is high (in logic level of "1") and DOWN signal is low (in logic level of "0"), M7 will be switched on and M6 is held off. In this condition, I9 enters into M7.…”

Section: Proposed Charge Pumpmentioning

confidence: 99%

A wide range delay locked loop for low power and low jitter applications

Estebsari

Gholami

Ghahramanpour

2017

Circuit Theory & Apps

Self Cite

View full text Add to dashboard Cite

show abstract

“…Charge pump based PLL (CPPLL) is broadly used in a wireless communication systems for frequency synthesis; especially in radio, telecommunications and other electronic applications due to its simple feedback system [1,2]. CPPLL is preferred because of low bias current [3,4], low static phase offset [5][6][7] and large system gain [8,9]. Furthermore, it performs the key role to ensure the stability of frequency synthesis [10,11].…”

Section: Introductionmentioning

confidence: 99%

“…With this conventional approach, the current mismatching features in these CPs [19,20] are scaled down to 2%. Besides, current mismatching is reduced to <1% in [6,8] by integrating operational amplifiers (Op-amp) technique. This method integrates a negative feedback amplifier along with op-amp where Op-amp controls the voltage node maintaining high amplifier gain and provides the advantage of the large input voltage of charge and discharge currents [21].…”

Section: Introductionmentioning

confidence: 99%

Nano CMOS Charge Pump for Readerless RFID PLL

Badal

Reaz

Bhuiyan³

2019

Informacije MIDEM

View full text Add to dashboard Cite

Readerless RFID has become more significant for reliable wireless communication. The Phase Locked Loop (PLL) is among the most crucial functional block in the Readerless RFID where the PLL performance greatly depends on the Charge Pump (CP). Conventional CP circuits suffer from current mismatching characteristics which generate phase offset and spurs in the PLL output signals. To overcome these problems, the CP current mismatch has to be minimized. An enhanced CP circuit with zero current mismatch is presented in this article adopting an ideal current mirror technique and an additional inverter to provide a rail-to-rail voltage. The post-layout simulation shows that the proposed CP maintains the steady current over a wide range of output voltage from 0.1-1.8 V consuming the substantially lower power of 0.178 µW. The CP circuit is designed in 130 nm CMOS process that operates at 1.8 V, and the core occupies 17 x 59.5 μm2. The proposed CP will be a good solution for low voltage, high-frequency PLL structure which suffers from poor performance.

show abstract

“…Recently, there has been an increased demand in radio frequency design [1][2][3]. One of the most important blocks in transceiver communication systems are the voltage controlled oscillators (VCOs) [4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Design of a 41.14–48.11 GHz Triple Frequency Based VCO

et al. 2019

Self Cite

View full text Add to dashboard Cite

Growing deployment of more efficient communication systems serving electric power grids highlights the importance of designing more advanced intelligent electronic devices and communication-enabled measurement units. In this context, phasor measurement units (PMUs) are being widely deployed in power systems. A common block in almost all PMUs is a phase locked oscillator which uses a voltage controlled oscillator (VCO). In this paper, a triple frequency based voltage controlled oscillator is presented with low phase noise and robust start-up. The VCO consists of a detector, a comparator, and triple frequency. A VCO starts-up in class AB, then steadies oscillation in class C with low current oscillation. The frequency of the VCO, which is from 13.17 GHz to 16.03 GHz, shows that the frequency is tripling to 41.14–48.11 GHz. Therefore, its application is not limited to PMUs. This work has been simulated in a standard 0.18 µm CMOS process. The simulated VCO achieves a phase noise of −99.47 dBc/Hz at 1 MHz offset and −121.8 dBc/Hz at 10 MHz offset from the 48.11 GHz carrier.

show abstract

A Novel Charge Pump with Low Current for Low-Power Delay-Locked Loops

Cited by 9 publications

References 9 publications

A wide range delay locked loop for low power and low jitter applications

A wide range delay locked loop for low power and low jitter applications

Nano CMOS Charge Pump for Readerless RFID PLL

Design of a 41.14–48.11 GHz Triple Frequency Based VCO

Contact Info

Product

Resources

About