Nano CMOS Charge Pump for Readerless RFID PLL

Abstract

Readerless RFID has become more significant for reliable wireless communication. The Phase Locked Loop (PLL) is among the most crucial functional block in the Readerless RFID where the PLL performance greatly depends on the Charge Pump (CP). Conventional CP circuits suffer from current mismatching characteristics which generate phase offset and spurs in the PLL output signals. To overcome these problems, the CP current mismatch has to be minimized. An enhanced CP circuit with zero current mismatch is presented in this article adopting an ideal current mirror technique and an additional inverter to provide a rail-to-rail voltage. The post-layout simulation shows that the proposed CP maintains the steady current over a wide range of output voltage from 0.1-1.8 V consuming the substantially lower power of 0.178 µW. The CP circuit is designed in 130 nm CMOS process that operates at 1.8 V, and the core occupies 17 x 59.5 μm2. The proposed CP will be a good solution for low voltage, high-frequency PLL structure which suffers from poor performance.

A high swing charge pump with current mismatch reduction for PLL applications

“…Eqs. (14), (15) and (16) indicate that loop3 is stable as its loop gain is below 0 dB. Moreover, when increases towards VDD, M1 operates in triode region, and M17 and CMRC1 are off.…”

“…This will result in the reference spur in the PLL output spectrum. Various design techniques have been proposed to directly improve the current matching [1,2,3,4,5,6,7,8,9,10,11,12] or to detect the current mismatch and then apply analog [13,14,15,16,17] or digital [18,19,20,21,22] calibration. The digital calibration technique [20] with a signed counter calibrates the current mismatch of CP by detecting the variation of steady-state phase offset and then changing the amplitude of CP charge or discharge current.…”