A novel cell structure for 4 M bit full feature EEPROM and beyond

Ajika, N.; Ohi, M.; Futatsuya, T.; Arima, Hideaki; Matsukawa, T.; Tsubouchi, N.

doi:10.1109/iedm.1991.235445

Cited by 4 publications

(2 citation statements)

References 2 publications

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“…2z In addition, the RTN-treated polysilicon film provides a better surface for the nucleation and growth of the silicon nitride and prevents the formation of a silicon-rich and defective layer between the native oxide and the silicon nitride layer. 22 The breakdown voltage histograms obtained by voltageramp tests conducted on smooth and rugged polysilicon film capacitors are shown in Fig. 8 and 9.…”

Section: Resultsmentioning

confidence: 99%

Physical and Electrical Characteristics of Thin Silicon Nitride Dielectric Films Deposited on Smooth and Rugged Polycrystalline Silicon after Rapid Thermal Nitridation

Mathews

Ditali

Fazan

1994

J. Electrochem. Soc.

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Rapid thermal nitridation (RTN) of the polycrystalline silicon (polysilicon) storage node prior to the deposition of the silicon nitride dielectric film has been investigated for capacitors with smooth and rugged electrodes. The nitridation process modifies the bonding arrangement on the polysilicon surface and leads to an enhancement of the nucleation and growth characteristics of the subsequent silicon nitride deposition process. This results in the growth of a thicker film on the RTN-treated surface for a given deposition time. For the same capacitance, the addition of the nitridation treatment reduces the leakage current through silicon nitride films deposited on smooth polysilicon while no such change in the leakage characteristics is seen for the rugged polysilicon film. However, for both smooth and rugged polysilicon electrodes, there is an improvement in the breakdown distribution as well as the time-dependent dielectric breakdown of the films with the nitridation process.

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Section: Resultsmentioning

confidence: 99%

Physical and Electrical Characteristics of Thin Silicon Nitride Dielectric Films Deposited on Smooth and Rugged Polycrystalline Silicon after Rapid Thermal Nitridation

Mathews

Ditali

Fazan

1994

J. Electrochem. Soc.

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“…It is known that the SSI has higher injection efficiency than the channel hot electron [5]- [7]. The cell has passed a 300-k program/erase (P/E) cycling endurance test and that can compete with other technologies [2], [8]- [10]. In addition, since the cell has enough margin to pass a 300-k times erase and program disturb test, error correcting circuitry would be not necessary in the circuit design [2].…”

Section: Introductionmentioning

confidence: 99%

High SCR Design for One-Transistor Split-Gate Full-Featured EEPROM

Chu

Lin

Wang

et al. 2004

IEEE Electron Device Lett.

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A high source-coupling ratio design for full-featured EEPROM composed of one-transistor split-gate cells with a cell area of less than 22 F 2 is proposed. This is in contrast to a traditional cell that requires an extra select transistor and is not area economic when compared to the new design cell. In this design, the cell adopts poly-poly Fowler-Nordheim tunneling to erase, and an inhibited source voltage is used for the unselected cell to achieve bit erase. It has demonstrated excellent program and erase disturb margins and passed 300 k program/erase (P/E) cycling test. It was found that after P/E cycling stress, the cell gains a better erase disturb immunity.

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