A Novel 1b Trench DRAM Cell With Raised Shallow Trench Isolation (RSTI)

Alsmeier,; Kelleher,; Beintner,; Haensch,; Mandelman,; Hoh,; Ninomiya,; Srinivasan, M. S.; Bronner,

doi:10.1109/vlsit.1997.623674

Cited by 7 publications

(3 citation statements)

References 3 publications

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“…When processing the shallow trench isolation (STI) after poly deposition [6,7], the cell requires a minimum area of 8F². This equals the minimum cell size of conventional DRAM cells, but this gain memory cell has the advantage of a significantly reduced storage capacitor.…”

Section: Process Integrationmentioning

confidence: 99%

DRAM Cell with High Signal Charge and Small Storage Capacitance Using the Gain Concept

2000

30th European Solid-State Device Research Conference

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Section: Process Integrationmentioning

confidence: 99%

DRAM Cell with High Signal Charge and Small Storage Capacitance Using the Gain Concept

2000

30th European Solid-State Device Research Conference

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“…The importance of this approach can be seen by comparing a typical 8F 2 cell layout [1] shown in Fig. 1(a) with a 6F 2 layout in Fig.…”

Section: Introductionmentioning

confidence: 99%

Extending KrF Lithography to 0.13 um sub-8F2 DRAM Technology: The Importance of Lithography-Centric Design

Bukofsky

Thomas²,

Kunkel³

2000

30th European Solid-State Device Research Conference

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Conventional optical lithography using a KrF excimer laser (λ =248 nm) is routinely used to manufacture DRAM technologies at ground rules as small as 0.15 µm. Due to the relative immaturity of ArF (λ =193 nm) lithography, it is desirable to continue to use KrF lithography for ground rules in the 0.13 µm regime. Simultaneously, continued DRAM chip scaling has led to investigation of open bit line architectures, whose theoretical minimum cell size is 4F 2 , where F is the minimum feature dimension. This has die size advantages over the 8F 2 minimum cell area of a conventional folded bit line cell.This cell architecture, combined with aggressive ground rule scaling, presents a unique challenge for optical lithography.In this paper, we discuss the evolution of sub-8F 2 cell designs relative to lithographic difficulty, and present examples of design sorting for best lithographic performance.

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“…4 shows schematically the process flow, as summarized in Table I. After forming the deep storage trench capacitor, the poly recess etch determining the buried strap depth is extended by about 0.3-0.4pm in order to accommodate space for the vertical transistor, followed by collar oxide removal and buried strap formation (Fig.…”

Section: Process Flowmentioning

confidence: 99%

A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

Gruening¹,

Radens²,

Mandelman³

et al.

International Electron Devices Meeting 1999. Technical Digest (Cat. No.99CH36318)

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Results are presented for a novel trench capacitor DRAM cell using a vertical access transistor along the storage trench sidewall which effectively decouples the gate length from the lithographic groundrule. A unique feature of this cell i s the _ _ vertical access transistor in the array which is self-aligned to the buried grap [ I ] connection of the storage trench (VERI BEST) and bounded by trench isolation oxide. The VERI BEST cell concept, process and electrical results obtained from 8F2 test cell arrays at 0.175pm groundrules are described in this paper.,

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A Novel 1b Trench DRAM Cell With Raised Shallow Trench Isolation (RSTI)

Cited by 7 publications

References 3 publications

DRAM Cell with High Signal Charge and Small Storage Capacitance Using the Gain Concept

DRAM Cell with High Signal Charge and Small Storage Capacitance Using the Gain Concept

Extending KrF Lithography to 0.13 um sub-8F2 DRAM Technology: The Importance of Lithography-Centric Design

A novel trench DRAM cell with a vertical access transistor and buried strap (VERI BEST) for 4 Gb/16 Gb

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