Results are presented for a novel trench capacitor DRAM cell using a vertical access transistor along the storage trench sidewall which effectively decouples the gate length from the lithographic groundrule. A unique feature of this cell i s the _ _ vertical access transistor in the array which is self-aligned to the buried grap [ I ] connection of the storage trench (VERI BEST) and bounded by trench isolation oxide. The VERI BEST cell concept, process and electrical results obtained from 8F2 test cell arrays at 0.175pm groundrules are described in this paper.,
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