A 0.135 μm/sup 2/ 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

Radens, C.; Gruening, U.; Mandelman, J.; Seitz, Michelle E.; Lea, D.; Casarotto, D.; Clevenger, L. A.; Nesbit, L.; Malik, R.; Halle, Scott; Kudelka, S.; Tews, H.; Divakaruni, R.; Sim, Jae Sung; Strong, A.; Tibbel, D.; Arnold, N.; Bukofsky, S.; Kunkel, G.; Bronner, G.

doi:10.1109/vlsit.2000.852777

Cited by 3 publications

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“…The greater difficulty of device miniaturization and the increasing cost of fabrication in the 0.1-m era lead, however, to a requirement for new memory cells which are smaller than . A trench-capacitor folded-bitline cell has recently been proposed [5]. However, it requires a vertical transistor along with an additional tight-pitch layer for its vertically folded bitline arrangement.…”

Section: Introductionmentioning

confidence: 99%

A low-impedance open-bitline array for multigigabit DRAM

Sekiguchi

Itoh

Takahashi³

et al. 2002

IEEE J. Solid-State Circuits

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The noise-generating mechanisms inherent in the open-bitline DRAM array using the 6 2 (: feature size) memory cells and techniques for reducing the noise are described. The sources of differential noise coupled to the paired bitlines laid out in two arrays are the p-well, cell plate, and the group of nonselected wordlines. It was found, by simulation and by experiment with a 0.13m 256-Mb test chip, that the level of noise is dramatically reduced by using a low-impedance array with careful layout featuring low-resistivity materials, tight bridging between pairs of adjacent arrays, and a small array, achieving a comparable level of noise to that seen in the twisted and folded-bitline array. On basis of these results, it turns out that the open-bitline array has a strong chance of revival in the multigigabit generation, as long as these noise reduction techniques are applied.

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Section: Introductionmentioning

confidence: 99%