A multigigabit DRAM technology with 6F/sup 2/ open-bitline cell, distributed overdriven sensing, and stacked-flash fuse

Takahashi, Tsuyoshi; Sekiguchi, Toshio; Takemura, Riichiro; Narui, S.; Fujisawa, Hironori; Miyatake, S.; Morino, Mario; Arai, K.; Yamada, S.; Shukuri, S.; Nakamura, M.; Tadaki, Yoshitaka; Kajigaya, K.; Kimura, K.; Itoh, K.

doi:10.1109/4.962294

Cited by 18 publications

(9 citation statements)

References 11 publications

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“…Using an overdrive circuit in the BLSA to temporarily apply a supply voltage higher than nominal is a well-known scheme [24] and has been adopted in commodity DRAM to reduce the sensing time. The overdrive complicates the delay and charge calculation due to the smaller sensing interval and the higher supply voltage.…”

Section: Blsa Overdrivementioning

confidence: 99%

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool

Shih

Luo

Yeh

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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DRAM renovation calls for a holistic architecture exploration to cope with bandwidth growth and latency reduction need. In this paper, we present DRAM area power timing (DArT), a DRAM area, power, and timing modeling tool, for array assembly and interface customization. Through proper design abstraction, our component-based modeling approach provides increased flexibility and higher accuracy, making DArT suitable for DRAM architecture exploration and performance estimation. We validate the accuracy of DArT with respect to the physical layout and circuit simulation of an industrial 68 nm commodity DRAM device as a reference. The experiment results show that the maximum deviations from the reference design, in terms of area, timing, and power, are 3.2%, 4.92%, and 1.73%, respectively. For an architectural projection by porting it to a 45 nm process, the maximum deviations are 3.4%, 3.42%, and 8.57%, respectively. The combination of modeling performance, flexibility, and accuracy of DArT allows us to easily explore new DRAM architectures in the future, including 3-D stacked DRAM.

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Section: Blsa Overdrivementioning

confidence: 99%

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool

Shih

Luo

Yeh

et al. 2014

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Because the size of a sense amplifier is more than 100x the size of a cell [193], modern DRAM designs fit in only enough sense amplifiers in a row to sense half a row of cells. To sense the entire row of cells, each subarray has bitlines that connect to two rows of sense amplifiers -one above and one below the cell array ( 1 and 2 in and is commonly used to achieve high density in modern DRAM chips [202,338]. A single row of sense amplifiers, which holds the data from half a row of activated cells, is also referred as a row buffer.…”

Section: Per-bank Refresh (Ref Pb )mentioning

confidence: 99%

Understanding and Improving the Latency of DRAM-Based Memory Systems

Chang

2017

Preprint

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“…Distributed overdriven sensing [7], [8] for low-voltage highspeed operation and alternate placement of SAs [11] are assumed, as is shown in Fig. 5.…”

Section: A Simulation Conditionsmentioning

confidence: 99%

“…A 0.13-m 256-Mb test chip (Fig. 13) was designed on the basis of the results of simulation and fabricated [7], [8]. The chip incorporates the proposed low-impedance array of Table II except that k .…”

Section: Experiments On An Open-bitline Arraymentioning

confidence: 99%

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A low-impedance open-bitline array for multigigabit DRAM

Sekiguchi

Itoh

Takahashi³

et al. 2002

IEEE J. Solid-State Circuits

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The noise-generating mechanisms inherent in the open-bitline DRAM array using the 6 2 (: feature size) memory cells and techniques for reducing the noise are described. The sources of differential noise coupled to the paired bitlines laid out in two arrays are the p-well, cell plate, and the group of nonselected wordlines. It was found, by simulation and by experiment with a 0.13m 256-Mb test chip, that the level of noise is dramatically reduced by using a low-impedance array with careful layout featuring low-resistivity materials, tight bridging between pairs of adjacent arrays, and a small array, achieving a comparable level of noise to that seen in the twisted and folded-bitline array. On basis of these results, it turns out that the open-bitline array has a strong chance of revival in the multigigabit generation, as long as these noise reduction techniques are applied.

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A multigigabit DRAM technology with 6F/sup 2/ open-bitline cell, distributed overdriven sensing, and stacked-flash fuse

Cited by 18 publications

References 11 publications

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool

Understanding and Improving the Latency of DRAM-Based Memory Systems

A low-impedance open-bitline array for multigigabit DRAM

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