A New Scaling Methodology For The 0.1 - 0.025/spl mu/m MOSFET

Fiegna,; Iwai,; Wada, Yasuhiro; Saito,; Sangiorgi,; Ricco,

doi:10.1109/vlsit.1993.760231

Cited by 44 publications

(20 citation statements)

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“…As we said before, this effect cannot be taken into account in our simulator. Nevertheless, Aoki et al [3] and Fiegna et al [5] showed fairly good subthreshold behavior of these devices. We should note that in Figs.…”

Section: Simulated I-v Curvesmentioning

confidence: 97%

“…Systematic investigations on the feasibility of devices with m have also been carried out [5]- [6]. These studies concluded that a new scaling method, different from Dennard's [7], is necessary to obtain such gate lengths.…”

mentioning

confidence: 99%

“…Fiegna et al [5] have studied the use of such a doping profile on very short-channel MOSFET's ( nm). They compared a MOSFET with an epitaxial layer over a high substrate to a uniformly doped MOS and to different SOI-MOSFET's, and 0018-9383/97$10.00 © 1997 IEEE found better behavior of the epitaxial MOSFET versus the other structures.…”

mentioning

confidence: 99%

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Study of the effects of a stepped doping profile in short-channel MOSFETs

López‐Villanueva

Gamiz

Roldán

et al. 1997

IEEE Trans. Electron Devices

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Abstract-The performance of a stepped doping profile for improving the short-channel behavior of a submicrometer MOS-FET has been analyzed in detail by using a quasi-two-dimensional (quasi-2-D) MOSFET simulator including inversion-layer quantization coupled with a one-electron Monte Carlo simulation. Several second-order effects, such as mobility degradation both by bulk-impurity and interface traps, carrier-velocity saturation, and channel-length modulation, have been included in the simulator. Very good agreement between experimental and simulated results are obtained for short-channel transistors. It has been shown that including a low-doped zone of convenient thickness next to the interface over a high-doping substrate improves both the electron mobility and the threshold voltage of the device, while avoiding short-channel effects. The use of simulation has allowed us to study certain kinds of devices without needing to make them.

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Section: Simulated I-v Curvesmentioning

confidence: 97%

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confidence: 99%

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Study of the effects of a stepped doping profile in short-channel MOSFETs

López‐Villanueva

Gamiz

Roldán

et al. 1997

IEEE Trans. Electron Devices

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“…It was expected that similar magnitude of I d -V d characteristics with suppression of the gate leakage current could be obtained using a physically-thick high-k gate film. 19 Thus, it had been vaguely proposed that such sub-3 nm thick gate insulators would be necessary for sub-100 nm gate length generations. However, the development of high-k gate insulators for MOSFETs had not been seriously undertaken, because it was not known at all if such small (sub-100 nm) gate length MOSFETs could operate successfully, and also, because alternative dielectric films at that time were found to have a much poorer interface.…”

Section: 12mentioning

confidence: 99%

High Dielectric Constant Materials for Nanoscale Devices and Beyond

Toriumi

Misra

2017

Electrochem. Soc. Interface

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Tremendous progress of CMOS integrated circuits have been conducted by the down-scaling or the miniaturization of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). Ten years, ago, the huge direct-tunneling gate leakage current through the thin gate SiO2 film of 1 nm thickness made it impossible to further scale-down the MOSFETs, and replacing the SiO2 by HfO2-based higher-dielectric constant (high-k) material was the solution. In this paper, the history of high-k gate insulator film development and two topics from recent research results regarding ferroelectricity and reliability are described.

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“…As one of the advantages of the thin-film DG-MOSFET is the possibility of using a very low doping concentration, hence reducing Coulomb scattering, we have chosen a transistor with a lightly doped epitaxial layer (with cm and a thickness of 15 nm) on a highly doped substrate (with N cm ) to compare with a bulk MOSFET of comparable performance. The channel is therefore lodged in a region with a low impurity concentration while the depletion region width is limited by the high impurity concentration in the substrate, thus minimizing short-channel effects [24], [25]. To make the comparison easy, the workfunction for the gate material in the DGMOSFET has been chosen so that the linearly-extrapolated threshold voltages are the same in both bulk and double-gate transistors.…”

Section: Numerical Calculationmentioning

confidence: 99%

Effects of the inversion-layer centroid on the performance of double-gate MOSFETs

López‐Villanueva

Cartujo-Cassinello

Gamiz

et al. 2000

IEEE Trans. Electron Devices

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Abstract-The role of the inversion-layer centroid in a double-gate metal-oxide-semiconductor field-effect-transistor (DGMOSFET) has been investigated. The expression obtained for the inversion charge is similar to that found in conventional MOSFET's, with the inversion-charge centroid playing an identical role. The quantitative value of this magnitude has been analyzed in volume-inversion transistors and compared with the value obtained in conventional MOSFETs. The minority-carrier distribution has been found to be even closer to the interfaces in volume-inversion transistors with very thin films, and therefore, some of the advantages assumed for these devices are ungrounded. Finally, the overall advantages and disadvantages of double-gate MOSFET's over their conventional counterparts are discussed.

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A New Scaling Methodology For The 0.1 - 0.025/spl mu/m MOSFET

Cited by 44 publications

References 1 publication

Study of the effects of a stepped doping profile in short-channel MOSFETs

Study of the effects of a stepped doping profile in short-channel MOSFETs

High Dielectric Constant Materials for Nanoscale Devices and Beyond

Effects of the inversion-layer centroid on the performance of double-gate MOSFETs

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