A New Programming Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated By GIDL Current

Lee, Jae-Duk; Lee, Chi-Kyung; Lee, Myung-Won; Kim, Han‐Soo; Park, Kyucharn; Lee, Won-Seong

doi:10.1109/.2006.1629481

Cited by 32 publications

(4 citation statements)

References 3 publications

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“…The first is the undesired injection of electrons from the channel to the storage layer of the victim cell determined by the positive WL bias involved in read and program operations. In this case, the V T change of the victim cell, which is properly said to come from a read disturb [7], [30], [31] or a program disturb [7], [30], [32], [33], depends on the cell memory state, on the possible presence in the cell tunnel-oxide of defects enhancing its low-field conduction and on cell position along the NAND string. The second main origin of changes in the V T of the victim cell is the modification of its electrostatic and conduction environment during read resulting from the change of the V T state of other cells in the array.…”

Section: B Disturb Errorsmentioning

confidence: 99%

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future. Index Terms-3-D NAND Flash arrays, Flash memories, semiconductor device modeling, semiconductor device reliability. I. INTRODUCTIONT HE NAND Flash technology has become, today, the undisputed leader in the nonvolatile memory market, largely overcoming the hard-disk drive (HDD) technology in terms of revenues [1]. This outcome has been determined by the capability of the NAND Flash solution to address quite a variety of applications better than any other storage technology, thanks to successful tradeoffs among cost, performance, and reliability. At the heart of all that there is, of course, the possibility to steadily increase the integration density of the NAND array and, in turn, the memory capacity per chip. This is clearly proved in Fig. 1 in terms of gross bit storage density (GBSD), i.e., the ratio between the storage capacity and the total chip area, of the NAND Flash chips presented at the IEEE International Solid-State Circuits Conference (IEEE ISSCC) since 2001 (see [2] for further details on the analysis methodology).Up to ∼2015, the GBSD increase was achieved, first of all, through a constant pace miniaturization of the memory cells

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Section: B Disturb Errorsmentioning

confidence: 99%

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Compagnoni

Spinelli

2019

IEEE Trans. Electron Devices

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“…2(b)] of three inhibit strings has the bias condition for BL and SSL of V cc , which is the same bias condition in conventional 2D NAND flash memory. [22][23][24][25] Bias condition for two remaining inhibit strings is specific to the 3D stack NAND flash memory. The BL biases for two remaining inhibit strings are 0 and V cc at a fixed SSL bias of 0 V. Thus the SSL device for three inhibit bias conditions is turned-off so that the body of the inhibit string is floated.…”

Section: Program Disturbance Due To Low Ssl V Thmentioning

confidence: 99%

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

Choe

Park

Lee

2013

Jpn. J. Appl. Phys.

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The program disturbance characteristic in the three-dimensional (3D) stack NAND flash was analyzed for the first time in terms of string select line (SSL) threshold voltage (V th ) and p-type body doping profile. From the edge word line (W/L) program disturbance, we can observe the boosted channel potential loss as a function of SSL V th and body doping profile for SSL device. According to simulation work, a high V th of the SSL device is required to suppress channel leakage during programming. When the body doping of the SSL device is high in the channel, there is a large band bending near the gate edge of the SSL adjacent to the edge W/L cell of boosted cell strings, which generates significantly electron-hole pairs. The generated electrons decreases the boosted channel potential, resulting in increase of program disturbance of the inhibit strings. Through optimization of the body doping profile of the SSL device, both channel leakage and the program disturbance are successfully suppressed for a highly reliable 3D stack NAND flash memory cell operation. #

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“…However, the aggressive scaling has given a rise to reliability issues including program disturbance and cell-tocell interference [1][2][3][4][5][6][7][8][9][10][11] and it gets more difficult to develop new flash memory products timely to market. Although several studies about analytic modeling of flash memory cell for SPICE simulation have been reported, 12,13) they are mainly focusing on either basic Fowler-Nordheim (FN) tunneling during a program/erase operations or interference between neighboring floating gates (FGs), which calls for more thorough investigations on phenomena at a string level with nanoscale devices and pitches.…”

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confidence: 99%

A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

Kang

Hahn

Park

et al. 2011

Jpn. J. Appl. Phys.

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This paper presents an analytic model for NAND flash array where channel coupling embodies. Channel coupling effect which is becoming a more serious issue in developing high-density flash memory devices should be effectively suppressed. By applying the coupling model to a 30-nm NAND flash product, the simulation showed a good agreement with the measurement results. Also, complex problems in scaled NAND flash memories could be accurately explained by circuit simulations. This evaluation will be useful in developing high-density multi-level cell (MLC) NAND flash technologies. #

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A New Programming Disturbance Phenomenon in NAND Flash Memory By Source/Drain Hot-Electrons Generated By GIDL Current

Cited by 32 publications

References 3 publications

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Body Doping Profile of Select Device to Minimize Program Disturbance in Three-Dimensional Stack NAND Flash Memory

A Compact Model for Channel Coupling in Sub-30 nm NAND Flash Memory Device

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