A new mechanism of pipeline defect formation in CMOS devices

Belgal, H.; Yuen, G.; Grohs, J.; Rozler, L.; Gee, H.; Broydo, S.; Wegener, H. A. R.; Owen, William H.; Drori, J.

doi:10.1109/relphy.1994.307807

Cited by 8 publications

(3 citation statements)

References 10 publications

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“…The excess junction reverse current is reduced, but another junction failure is observed in association with crystal defectivity, consisting of a source-to-drain leakage of transistors due to pipeline defects. Pipeline defects have been widely reported in bipolar devices [2] and recently also in complementary-metal-oxide-semiconductor (CMOS) technology [3,4]. This failure is explained by an anomalous dopant diffusion along the defect, making the defect act as a resistive path.…”

Section: Introductionmentioning

confidence: 99%

Crystal defects and junction properties in the evolution of device fabrication technology

Mica

Polignano

Carnevale

et al. 2002

J. Phys.: Condens. Matter

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In this paper, the correlation between dislocation density and transistor leakage current is demonstrated. The stress evolution and the generation of defects are studied as a function of the process step, and experimental evidence is given of the role of structure geometry in determining the stress level and hence defect formation. Finally, the role of high-dose implantations and the related silicon amorphization and recrystallization is investigated.

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Section: Introductionmentioning

confidence: 99%

Crystal defects and junction properties in the evolution of device fabrication technology

Mica

Polignano

Carnevale

et al. 2002

J. Phys.: Condens. Matter

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“…It was widely reported that crystal defects and specifically dislocations are very harmful in present silicon devices, where they can be responsible for electrical failures due to a junction excess leakage current (1)(2)(3) or to a source-to-drain junction piping and hence for a transistor leakage current (see for instance (4)(5)(6)(7)(8)(9)(10)). Mechanical stress is obviously an important quantity for dislocation formation, and accurate models to calculate the mechanical stress in the process flow are available (11).…”

Section: Introductionmentioning

confidence: 99%

(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances

et al. 2013

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This paper collects the results of some experiments aimed at investigating the physical mechanisms of defect generation in devices. It is shown that suitable limits for the mechanical stress can be defined to prevent defect generation. In addition, a high temperature stress release annealing can be beneficial for stress reduction and defect prevention. The annealing of implanted layers may result in crystal defect formation even with no contribution from mechanical stress. In this case, the silicon surface plays a relevant role in reducing the point defect concentration and hence the nucleation of extended defects. In the annealing process of high energy implantations, the most damaged region is far from the wafer surface. Under these conditions, impurities in the silicon substrate play a relevant role in determining the resulting defect morphology. The presence of interstitial oxygen forces defects to grow along <110> directions parallel to the silicon surface, thus preventing them to reach the device region.

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“…It was widely reported that crystal defects and specifically dislocations are very harmful in present silicon devices, where they can be responsible for electrical failures due to a junction excess leakage current (1)(2)(3) or to a source-to-drain junction piping and hence for a transistor leakage current (see for instance (4)(5)(6)(7)(8)(9)(10). It would be therefore very important to be able to identify critical conditions for defects formation by numerical models, and so to prevent the defect-related failures.…”

Section: Introductionmentioning

confidence: 99%

Mechanical Stress and Defect Formation in Device Processing

Polignano¹,

Carnevale²,

Fantini³

et al. 2006

ECS Trans.

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In this work we address the problem of estimating the mechanical stress and the related risk of crystal defect generation in a complex device process. The validity of numerical calculations of the mechanical stress developed in the device process flow is assessed by comparing the simulation results with the electrical measurements of test structures designed to monitor the dislocations formation and of other silicon strain sensitive structures. The results show that based upon numerical calculations it is possible to define mechanical stress criteria for preventing defect generation. By using this sort of criteria, potentially dangerous process variations can be easily identified. This method is quite general and can be applied to any device process flow. On the other hand, by comparing the electrical results of structures prone to defect generation and of stress-sensitive transistors with a non-critical geometry for defect generation, it is shown that after defect nucleation the elastic stress in non-critical structures and the defect-related failure fraction in critical structures may evolve into opposite directions. Therefore, suitable stress criteria are needed at all the levels in the process flow where crystal damage may cause defect nucleation. In this study it is also pointed out that a high temperature stress release annealing can be beneficial for stress reduction and defect prevention, but its position in the process flow is critical.

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A new mechanism of pipeline defect formation in CMOS devices

Cited by 8 publications

References 10 publications

Crystal defects and junction properties in the evolution of device fabrication technology

Crystal defects and junction properties in the evolution of device fabrication technology

(Invited) Defect Generation in Device Processing and Impact on the Electrical Performances

Mechanical Stress and Defect Formation in Device Processing

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