A New Level Shifter with Low Power in Multi-Voltage System

Zhang, Bo; Liang, Liping; Wang, Xingjun

doi:10.1109/icsict.2006.306488

Cited by 25 publications

(22 citation statements)

References 5 publications

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“…The signal IN_B shows the contention problem in case of the conventional scheme given in [11], this causes some delay on the output signal OUT while going high. This problem is taken care by the conventional level shifter scheme given in [12]. When input IN goes low, the signal IN_B shows the same contention in both the conventional schemes [11,12] and is more in case of conventional scheme [12], this causes IN_B to take much more time to go high and the output node OUT to go low.…”

Section: Results and Analysismentioning

confidence: 97%

“…This also has impact on power because the node VS needs to be pre charged to VDDH from a lower voltage level that is below VDDH-2Vtn. Another possible solution for the existing problem given in [12] as shown in Figure 3.This scheme also works similar to the scheme given in [11] except the node VS reaches VDDH-Vtn when input IN is low. Though the scheme in [12] removes contention, but is having limitation in terms of wide range of voltage translation and this scheme does not work well for the voltage VDDL=0.45V as shown in Figure 8.…”

Section: Conventional Level Shiftermentioning

confidence: 82%

“…The timing wave forms of the proposed scheme, the conventional scheme [11] and the conventional scheme [12] for VDDL=0.5V and VDDH=1.05V are shown in Figure 6. This is the case where all three schemes work well; these values are taken for the apple to apple comparison.…”

Section: Results and Analysismentioning

confidence: 99%

“…The possible solutions for the existing problem given in [11,12] are suffering from performance degradation. So In this paper, a new voltage up level shifter has been proposed and designed in 45nm CMOS technology which permits a wide range of voltage translation with reduced power and improved performance.…”

Section: Introductionmentioning

confidence: 99%

“…The conventional level shifter circuits proposed in [1][2][3][4][5][6][7][8][9][10][11][12] suffer from the contention between the pull up and pull down transistors which leads to the increase in delay and also the power consumption because of the DC leakage path from the power source to ground. At lower core voltages, particularly below 1V, the problem of contention becomes severe.…”

Section: Introductionmentioning

confidence: 99%

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Voltage up level shifter with improved performance and reduced power

Dwivedi

Potladhurthi

2012

2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

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In Ultra Deep Sub Micron technology nodes, particularly 45nm and below, multiple power supplies are needed to achieve optimum performance. In such SoC's, level shifters play an important role in translating the signals from one voltage level to another. The conventional level shifters suffer from the contention between the pull up and pull down transistors which leads to the increase in delay and the power consumption, so the existing techniques are unable to address the requirement of wide range of voltage translation at lower core voltages below 1V. In this paper a new voltage up level shifter has been proposed and designed for up shifting the signal levels for a wide range of voltage levels. This circuit consists of level shifter block and reference voltage generation circuit, which generates a constant voltage depending up on the ratio between pre charge rate and discharge rate to avoid the contention between pull up and pull down transistors of level shifter block. It results in faster transition and less power compared to earlier level shifters. The proposed circuit is designed in 45nm CMOS technology using PO-WERSPICE, consumes only 89.4nw power and gives an average delay of 70ps at Vin =0.45V, VDDH=1.05V while occupying an area of 1.67um2.

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Section: Results and Analysismentioning

confidence: 97%

Section: Conventional Level Shiftermentioning

confidence: 82%

Section: Results and Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Voltage up level shifter with improved performance and reduced power

Dwivedi

Potladhurthi

2012

2012 25th IEEE Canadian Conference on Electrical and Computer Engineering (CCECE)

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IO circuit design for 2.5D through‐silicon‐interposer interconnects

Jawed

Afridi

Anjum

et al. 2016

Circuit Theory & Apps

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This paper presents four topologies of voltage-mode un-terminated IO cells in 28-nm CMOS for singleended rail-to-rail signaling over a passive interposer die in 2.5D configuration for >1Gbps data rates. The presented design explores the existing IO design-space from a 2.5D viewpoint, optimizing existing topologies from area, speed, power and protection perspectives, with a higher degree of configurability in the form of pre-emphasis and slew-rate control. The transmitter (TX) embeds pre-emphasis to enhance high-frequency components of the signal for longer low-pass natured channels. The TX also implements slew-rate control to minimize reflections on shorter channels because of impedance discontinuities and also to minimize simultaneous switching noise. Level-shifting capability embedded in the receiver (RX) enables multi-technology interfacing where different dies are signaling at their core voltages (range: 0.7 V-1.8 V) instead of following a particular signaling standard. The measurement results of the transceivers, over a interposer of length of 3.5 mm, demonstrate ±5% duty-cycle distortion with 700 μW at 500 MHz/0.8-V-signaling on the channel with jitter of 20 ps, ±10% duty-cycle distortion with 1.8 mW at 1Gbps/0.9-V signaling with jitter of 20 ps, ±10% duty-cycle distortion with 2 mW at 2Gbps/0.7-V signaling for 1-V receiver core voltage with a jitter of 10 ps. of limiter material or functional errors because of electro-thermal coupling or excessive leakage currents which can form a positive feedback loop with the temperature leading to thermal run-away problem [10,11]. Moreover, the thermal expansion coefficients of TSV material and substrate are different, which can result in large temperature induced mechanical stress again leading to nonuniform distribution of delay across the area [5].Recently, 2.5D IC stacking has emerged as a viable alternative because of its higher mechanical and thermal reliability with a comparable interconnect density [10,12,13]. Several flip-chip dies are attached with fine-pitch micro-bumps to a single passive interposer die also known as throughsilicon-interposer (TSI) communication. This interposer die allows connections between adjacently placed multi-technology dies as well as connections to the package, providing low interconnect delay, high-bandwidth, multi-technology interfacing and reduced ESD protection requirements for die-to-die connections [14]. Moreover, although incurring the cost of adding a passive Si interposer, TSI avoids the issues faced by TSV based 3D configuration related to the high-temperature gradients because of poor thermal distribution, difficult IO planning, large keep-out areas and reliable manufacturing [10,13,15,16]. When compared with traditional backplane through-PCB interconnections which span lengths of few inches (>25 cm), TSI interconnects are much shorter (few mm) in length [2], which is one of the main reasons for their enhanced performance. For example, at 5 Gbps a 25-cm-long PCB track suffers from approximately 20-dB additional channel l...

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