The proposed novel FinFET 7T cell involves the breaking-up of feedback between the true storing nodes that enhances the writability of the cell at ultra-low voltage (ULV) power supply without boosted supply and write assist at 20nm technology node. Proposed 7T achieves improved hold static noise margin (HSNM) as compared to the conventional upsized 5T (U5T) cell. The write trip point (WTP) is 16.2% lower than the U5T WTP at 100mV. The read power consumption is reduced by 13.7% with similar write power consumption of U5T. The read decoupling and feedback cutting makes proposed 7T more immune to process variations in sub-threshold regime.
A novel single-ended boost-less 7T static random access memory cell with high write-ability and reduced read failure is proposed. Proposed 7T cell utilizes dynamic feedback cutting during write/read operation. The 7T also uses dynamic read decoupling during read operation to reduce the read disturb. Proposed 7T writes "1" through one NMOS and writes "0" using two NMOS pass transistors. The 7T has mean (μ) of 222.3 mV (74.1 % of supply voltage) for write trip point where 5T fails to write "1" at 300 mV. It gives mean (μ) of 276 mV (92 % of supply voltage) for read margin, while 5T fails due to read disturb at 300 mV. The hold static noise margin of 7T is maintained close to that of 5T. The read operation of 7T is 22.5 % faster than 5T and saves 10.8 % read power consumption. It saves 36.9 % read and 50 % write power consumption as compared to conventional 6T. The novel design of proposed 7T consumes least read power and achieves the lowest standard deviation as compared to other reported SRAM cells. The power consumption of 1 kb 7T SRAM array during read and write operations is 0.70× and 0.65×, respectively, of 1 kb 6T array. The techniques used by the proposed 7T SRAM cell allow it to operate at ultralow-voltage supply without any write assist in UMC 90 nm technology node. Future applications of the proposed 7T cell can potentially be in low-voltage, ultra-low-
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