A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors

Ulbricht, Markus; Scholzel, Mario; Koal, Tobias; Vierhaus, Heinrich Theodor

doi:10.1109/ddecs.2011.5783067

Cited by 11 publications

(5 citation statements)

References 12 publications

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“…However, the random (irregular) structure of logic cores makes the implementation of BISR capabilities more difficult. This is the main reason why only ad hoc methods exist in this area and the BISR architecture was introduced only for specific cores [5]- [7] and not as a generic architecture. Research was conducted to estimate the reliability of BISR architectures (considered again in the context of superscalar processors) [8].…”

Section: Related Workmentioning

confidence: 99%

Generic built-in self-repair architectures for SoC logic cores

Baláž

Kristofik

Fischerova

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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The built-in self-repair (BISR) concept is utilized and proven by industry mainly in regular structures of systemon-chips (SoCs) memory cores. On the other hand, the idea of self repair concept for logic cores introduced and developed in several papers is relatively new, as the irregular structure of these types of cores represents a serious limitation. However, there is a need of a complex BISR architecture that can be widely used on different types of logic cores in order to support further the reliability of SoCs. This paper presents a generic BISR architecture based on reconfigurable logic blocks (RLBs) applicable for any logic core inside a SoC together with in detail defined basic requirements guiding the architecture development and also algorithms handling fault detection and localization procedure.

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Section: Related Workmentioning

confidence: 99%

Generic built-in self-repair architectures for SoC logic cores

Baláž

Kristofik

Fischerova

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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“…It has been addressed mainly for permanent errors, such as those produced by manufacturing defects or ageing. Approaches include Design for Test (DfT) techniques, such as scan-based BIST (Built-In Self Test) [11], Software-Based Self-Test [12], or a combination of both [13]. In complex circuits, BIST structures are often included on chip to support test functions and can also be used in the field.…”

Section: Related Workmentioning

confidence: 99%

Microprocessor Error Diagnosis by Trace Monitoring Under Laser Testing

Pena-Fernandez

Lindoso

Entrena

et al. 2021

IEEE Trans. Nucl. Sci.

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This work explores the diagnosis capabilities of the enriched information provided by microprocessors trace subsystem combined with laser fault injection. Laser fault injection campaigns with delimited architectural regions have been accomplished on an ARM Cortex-A9 device. Experimental results demonstrate the capability of the presented technique to provide additional information of the various error mechanisms that can happen in a microprocessor. A comparison with radiation campaigns presented in previous work is also discussed, showing that laser fault injection results are in good agreement with neutron and proton radiation results.

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“…Another technique able to obtain a good diagnostic resolution with a low hardware overhead is proposed in [14]; this technique combines scan and SBST and it is oriented to the test of VLIW processors. The specific characteristic of that approach is the ability to detect faults inside the processor functional units, obtained by loading the same test patterns directly to the test registers of all the computational domains.…”

Section: Related Workmentioning

confidence: 99%

“…In [2] a new cost-effective approach is presented: the approach is based on the automatic generation of a diagnostic test set using an existing post-production test set; the authors propose to improve that set using an evolutionary method. In [9] the authors present a new diagnostic method for VLIW processors, based on scan-based BIST and SBST, aimed at a good diagnostic resolution with low hardware overhead. Software-based BIST is introduced for a fast diagnosis of the Computational Domains of the processor.…”

Section: Related Workmentioning

confidence: 99%

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On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

Sabena

Sterpone

Reorda

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this chapter we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while minimizing the test duration and the test code size. Moreover, using this method, a set of small SBST programs can be generated aimed at the diagnosis of the VLIW processor. Experimental results gathered on a case study show the effectiveness of the proposed approach.Keywords: SBST, VLIW processor, Fault Simulation, Fault Diagnosis. IntroductionThe continuous scaling in the semiconductor fabrication process combined with the progressive growth of the integrated circuits operation frequency pushes processor cores to face more difficult testability problems. Furthermore, several phenomena such as metal migration or aging become more likely, thus increasing the occurrence of permanent faults in the generic system, in particular during the circuit operational phase. For these reasons, in order to provide high fault coverage with acceptable costs, new test solutions are being investigated and evaluated (e.g., in terms of silicon area overhead, required test infrastructure and test time). Software-Base Self-Test (SBST) has been demonstrated to be a promising and effective approach for the test of processors and processor-based systems [1]. The SBST main idea is to generate test programs to be executed by the processor under test, able to fully stimulate the processor itself or other components belonging to the system, and to detect possible faults by looking at the produced results. The SBST technique does not require any additional hardware; therefore, the whole test cost is reduced and no performance penalty is introduced. Moreover, the SBST technique allows at-speed testing and can be easily used even for on-line test purposes. Hence,

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A new hierarchical built-in self-test with on-chip diagnosis for VLIW processors

Cited by 11 publications

References 12 publications

Generic built-in self-repair architectures for SoC logic cores

Generic built-in self-repair architectures for SoC logic cores

Microprocessor Error Diagnosis by Trace Monitoring Under Laser Testing

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

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