The built-in self-repair (BISR) concept is utilized and proven by industry mainly in regular structures of systemon-chips (SoCs) memory cores. On the other hand, the idea of self repair concept for logic cores introduced and developed in several papers is relatively new, as the irregular structure of these types of cores represents a serious limitation. However, there is a need of a complex BISR architecture that can be widely used on different types of logic cores in order to support further the reliability of SoCs. This paper presents a generic BISR architecture based on reconfigurable logic blocks (RLBs) applicable for any logic core inside a SoC together with in detail defined basic requirements guiding the architecture development and also algorithms handling fault detection and localization procedure.
The paper presents a software tool that demonstrates principles of RAM memory testing and of the memory BIST structure. The MemBIST software tool automatically generates built-in self-test blocks for a given memory matrix as a VHDL model of the whole system. As a complement to the BIST structure generator, a module for visualisation of selected RAM memory fault models, March C-test algorithm as well as a memory self-testing architecture principle is a part of the tool. The developed system was implemented as a Java applet what means its good compatibility regarding different hardware and operating system platforms, its safety and accessibility while it is placed on Internet. The presented MemBIST applet is useful as an educational tool and a training tool in built-in selftesting for RAM memories.
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