Automated Generation of Built-In Self-Repair Architectures for Random Logic SoC Cores

Dobai, Roland; Baláž, Marcel; Fischerova, M.

doi:10.1109/dsd.2012.29

Cited by 4 publications

(4 citation statements)

References 7 publications

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“…The proposed RLB architecture is depicted in Figure 3. The number of RLBs present in the core is not limited, moreover the number is a very specific parameter of each BISR realization and a proper structural analysis of the core should precede [10] (the structural analysis of logic cores is beyond the scope of the paper).…”

Section: B Generic Bisr Architecturementioning

confidence: 99%

“…However, the impact of unassigned logic gates on the BISR architecture was not investigated. The second work [10] is automatic generation of BISR architectures for random logic cores where the generation based on the genetic algorithm is guided by two key characteristics of the core: mean time to failure and area overhead. It presents the fully automated handling of arbitrary random logic cores and the possibility to generate architectures based on various BISR principles.…”

Section: Related Workmentioning

confidence: 99%

“…There are only two known works conducted to analyze the structure of random logic cores [9], [10]. The first work [9] has assigned into FBs most of the logic gates of the benchmark circuits.…”

Section: Related Workmentioning

confidence: 99%

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Generic built-in self-repair architectures for SoC logic cores

Baláž

Kristofik

Fischerova

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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The built-in self-repair (BISR) concept is utilized and proven by industry mainly in regular structures of systemon-chips (SoCs) memory cores. On the other hand, the idea of self repair concept for logic cores introduced and developed in several papers is relatively new, as the irregular structure of these types of cores represents a serious limitation. However, there is a need of a complex BISR architecture that can be widely used on different types of logic cores in order to support further the reliability of SoCs. This paper presents a generic BISR architecture based on reconfigurable logic blocks (RLBs) applicable for any logic core inside a SoC together with in detail defined basic requirements guiding the architecture development and also algorithms handling fault detection and localization procedure.

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Section: B Generic Bisr Architecturementioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

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Generic built-in self-repair architectures for SoC logic cores

Baláž

Kristofik

Fischerova

2014

17th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems

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“…It was successfully applied on the benchmark circuits assigning most of their logic gates to FBs but the impact of unassigned gates on the BISR architecture was not investigated. The method presented in [11] uses genetic algorithm to search the problem space and to find FBs inside of any arbitrary combinational logic core. The drawback of the method is the size of the created FBs for benchmark circuits.…”

Section: A Core Partitioning Processmentioning

confidence: 99%

Built-in self-repair architecture generator for digital cores

Kristofik

Baláž

2016

2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits &Amp; Systems (DDECS)

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Built-in self-repair (BISR) concept is widely utilized and proven by industry to increase the reliability of regular structures such as memory cores. The idea of using this concept in mostly irregular structures such as logic cores is quite new and represents a challenging task with many problems involved; e.g. the identification of regular parts in a logic core suitable for reconfiguration, excessive area overhead and complexity of reconfiguration logic, etc. Current promising solutions for an efficient BISR architecture design are based on reconfigurable logic blocks (RLBs). In this paper, a new automated generator of the adequate BISR reconfiguration architecture is proposed. The generation process input is a simple description of arbitrary logic core already divided into RLBs and the generated output is the synthesizable HDL description of the BISR architecture for the core.

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