Generic built-in self-repair architectures for SoC logic cores

Abstract

The built-in self-repair (BISR) concept is utilized and proven by industry mainly in regular structures of systemon-chips (SoCs) memory cores. On the other hand, the idea of self repair concept for logic cores introduced and developed in several papers is relatively new, as the irregular structure of these types of cores represents a serious limitation. However, there is a need of a complex BISR architecture that can be widely used on different types of logic cores in order to support further the reliability of SoCs. This paper presents a generic BISR architecture based on reconfigurable logic blocks (RLBs) applicable for any logic core inside a SoC together with in detail defined basic requirements guiding the architecture development and also algorithms handling fault detection and localization procedure.

Built-in self-repair architecture generator for digital cores

“…The goal is not only to divide as much of the logic into FBs as possible but also to find FBs of adequate size to keep the area overhead of reconfiguration logic reasonably low. The previous research proved the average FB size should be at least 100 transistors [6], [7]. The core partitioning process can be performed relatively easily in specific cores with identical parts, e.g.…”

“…Switching of RLB blocks is usually carried out by 2-way switches with different implementations [4], [6].…”